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| 1 | +// -*- mode: c++; indent-tabs-mode: nil; -*- |
| 2 | + |
1 | 3 | // Based on the this: |
2 | 4 | /********************************************* |
3 | 5 | * vim:sw=8:ts=8:si:et |
@@ -166,29 +168,10 @@ template <class CSPin> class ENC28J60 |
166 | 168 | //pinMode(ENC28J60_CONTROL_CS, OUTPUT); |
167 | 169 | CSPin::modeOutput(); |
168 | 170 |
|
169 | | - //pinMode(SPI_MOSI, OUTPUT); |
170 | | - Pin::SPI_MOSI::modeOutput(); |
171 | | - //pinMode(SPI_SCK, OUTPUT); |
172 | | - Pin::SPI_SCK::modeOutput(); |
173 | | - //pinMode(SPI_MISO, INPUT); |
174 | | - Pin::SPI_MISO::modeInput(); |
175 | | - |
176 | | - //digitalWrite(SPI_MOSI, LOW); |
177 | | - Pin::SPI_MOSI::clear(); |
178 | | - |
179 | | - //digitalWrite(SPI_SCK, LOW); |
180 | | - Pin::SPI_SCK::clear(); |
181 | | - |
182 | | - /*DDRB |= 1<<PB3 | 1<<PB5; // mosi, sck output |
183 | | - cbi(DDRB,PINB4); // MISO is input |
184 | | - // |
185 | | - cbi(PORTB,PB3); // MOSI low |
186 | | - cbi(PORTB,PB5); // SCK low |
187 | | - */ |
188 | | - // initialize SPI interface |
189 | | - // master mode and Fosc/2 clock: |
190 | | - ::Register::SPCR = (1 << SPE) | (1 << MSTR); |
191 | | - SPSR |= (1<<SPI2X); |
| 171 | + // Note the old code cleared MOSI and SCK, SPI::init() |
| 172 | + // currently doesn't. |
| 173 | + SPI::init(0, true); |
| 174 | + |
192 | 175 | // perform system reset |
193 | 176 | WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); |
194 | 177 | _delay_ms(50); |
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