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VPR fails to PnR #127

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abdullahyildiz opened this issue Aug 30, 2021 · 0 comments

abdullahyildiz commented Aug 30, 2021

I get the following error when I run vpr_blif flow for counter benchmark and FPGA1212_SOFA_HD_PNR architecture:

Built a inner-column/row tile-to-tile direct from clb[11][11]terminate called after throwing an instance of 'VprError'
  what():  in load_one_net_delay: Traceback for net 3 does not exist.

I looked over the log files but it didn't help so far. The architecture file seems OK.

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