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I want to know if there's way I can do exactly what SOFA is doing but not use skywater standard cells. Is there a way I can just select which standard cell library to use?
The text was updated successfully, but these errors were encountered:
Sure, you can do that.
You will have to makes changes to a couple of files
./FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml defines the standard cell mapping (sky130_fd_sc_* for Sky130) change that to your preferred standard cell.
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/sc_verilog this directory also has few standard cells defined please change that as well.
With those changes, you should be able to generate a new Verilog netlist with your preferred standard cell library using OpenFPGA.
I want to know if there's way I can do exactly what SOFA is doing but not use skywater standard cells. Is there a way I can just select which standard cell library to use?
The text was updated successfully, but these errors were encountered: