From 1b50f1eba4d236574acc85f3889a40b45079f47a Mon Sep 17 00:00:00 2001 From: Faisal Puthuparackat Date: Fri, 4 Jun 2021 12:38:02 +0530 Subject: [PATCH 1/3] Fix filesize calculation on MacOS. Stat output doesn't gurantee st_size is the first field. Parse the result for st_size instead. --- k210-freertos/BUILD.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/k210-freertos/BUILD.sh b/k210-freertos/BUILD.sh index d642029..53ed3b4 100755 --- a/k210-freertos/BUILD.sh +++ b/k210-freertos/BUILD.sh @@ -439,7 +439,7 @@ fi if [ $? -eq 0 ]; then if [ "${machine}" == "MacOS" ]; then - FILESIZE=$(stat -s MicroPython.bin | cut -d' ' -s -f 1 | cut -d'=' -s -f 2) + FILESIZE=$(stat -s MicroPython.bin | tr ' ' '\n' | grep st_size| cut -d= -f2) else FILESIZE=$(stat -c%s MicroPython.bin) fi From 7fdb01ce216458da048bc8d1008fdc24ff7451f6 Mon Sep 17 00:00:00 2001 From: Faisal Date: Thu, 1 Dec 2022 22:54:55 +0530 Subject: [PATCH 2/3] Add docker build support - testing --- .dockerignore | 1 + docker/Dockerfile | 3 +++ docker/build.sh | 3 +++ docker/run.sh | 3 +++ k210-freertos/k210_env | 2 +- 5 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 .dockerignore create mode 100644 docker/Dockerfile create mode 100755 docker/build.sh create mode 100755 docker/run.sh diff --git a/.dockerignore b/.dockerignore new file mode 100644 index 0000000..6b8710a --- /dev/null +++ b/.dockerignore @@ -0,0 +1 @@ +.git diff --git a/docker/Dockerfile b/docker/Dockerfile new file mode 100644 index 0000000..54f492d --- /dev/null +++ b/docker/Dockerfile @@ -0,0 +1,3 @@ +from debian:stable-slim + +RUN apt-get update && apt-get install -qyy git cmake build-essential xz-utils python3 python3-serial wget zip libncurses5-dev diff --git a/docker/build.sh b/docker/build.sh new file mode 100755 index 0000000..3c7445f --- /dev/null +++ b/docker/build.sh @@ -0,0 +1,3 @@ +#! /bin/bash + +docker build -t k210mpy . diff --git a/docker/run.sh b/docker/run.sh new file mode 100755 index 0000000..1a85f6d --- /dev/null +++ b/docker/run.sh @@ -0,0 +1,3 @@ +#! /opt/local/bin/bash + +docker run -it --rm -v $(PWD)/..:/src k210mpy bash diff --git a/k210-freertos/k210_env b/k210-freertos/k210_env index 783952e..ae670e7 100644 --- a/k210-freertos/k210_env +++ b/k210-freertos/k210_env @@ -1 +1 @@ -export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/home/LoBo2_Razno/K210_razvoj/MicroPython_K210_LoBo/k210-freertos/../kendryte-toolchain/bin/ +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/src/k210-freertos/../kendryte-toolchain/bin/ From 4aeb9862795e46f51da71df97aff91f8851c5cc2 Mon Sep 17 00:00:00 2001 From: Faisal Date: Fri, 2 Dec 2022 09:40:04 +0530 Subject: [PATCH 3/3] Change Kboot to a submodule --- .gitmodules | 3 + Kboot | 1 + Kboot/CMakeLists.txt | 32 - Kboot/Kboot.md | 182 - Kboot/README.md | 204 - Kboot/cmake/CMakeLists.txt | 44 - Kboot/cmake/README.md | 3 - Kboot/cmake/common.cmake | 43 - Kboot/cmake/compile-flags.cmake | 67 - Kboot/cmake/dump-config.cmake | 22 - Kboot/cmake/executable.cmake | 45 - Kboot/cmake/fix-9985.cmake | 3 - Kboot/cmake/ide.cmake | 7 - Kboot/cmake/macros.cmake | 72 - Kboot/cmake/macros.internal.cmake | 12 - Kboot/cmake/toolchain.cmake | 51 - Kboot/lds/bootloader_hi.ld | 263 -- Kboot/lds/bootloader_lo.ld | 265 -- Kboot/lds/kendryte.ld | 263 -- Kboot/lib/CMakeLists.txt | 28 - Kboot/src/bootloader_hi/README.md | 205 - Kboot/src/bootloader_hi/crt.S | 23 - Kboot/src/bootloader_hi/fpioa.c | 4932 -------------------- Kboot/src/bootloader_hi/gpiohs.c | 110 - Kboot/src/bootloader_hi/include/config.h | 6 - Kboot/src/bootloader_hi/include/encoding.h | 1325 ------ Kboot/src/bootloader_hi/include/fpioa.h | 1035 ---- Kboot/src/bootloader_hi/include/gpiohs.h | 256 - Kboot/src/bootloader_hi/include/platform.h | 98 - Kboot/src/bootloader_hi/include/sha256.h | 130 - Kboot/src/bootloader_hi/include/spi.h | 123 - Kboot/src/bootloader_hi/include/sysctl.h | 886 ---- Kboot/src/bootloader_hi/main.c | 562 --- Kboot/src/bootloader_hi/sha256.c | 136 - Kboot/src/bootloader_lo/crt.S | 21 - Kboot/src/bootloader_lo/include/encoding.h | 1325 ------ Kboot/src/bootloader_lo/include/platform.h | 98 - Kboot/src/bootloader_lo/include/spi.h | 123 - Kboot/src/bootloader_lo/include/sysctl.h | 886 ---- Kboot/src/bootloader_lo/main.c | 191 - docker/run.sh | 4 +- k210-freertos/.config | 7 +- micropython/mpy-cross/Makefile | 2 +- 43 files changed, 11 insertions(+), 14083 deletions(-) create mode 100644 .gitmodules create mode 160000 Kboot delete mode 100644 Kboot/CMakeLists.txt delete mode 100644 Kboot/Kboot.md delete mode 100644 Kboot/README.md delete mode 100644 Kboot/cmake/CMakeLists.txt delete mode 100644 Kboot/cmake/README.md delete mode 100644 Kboot/cmake/common.cmake delete mode 100644 Kboot/cmake/compile-flags.cmake delete mode 100644 Kboot/cmake/dump-config.cmake delete mode 100644 Kboot/cmake/executable.cmake delete mode 100644 Kboot/cmake/fix-9985.cmake delete mode 100644 Kboot/cmake/ide.cmake delete mode 100644 Kboot/cmake/macros.cmake delete mode 100644 Kboot/cmake/macros.internal.cmake delete mode 100644 Kboot/cmake/toolchain.cmake delete mode 100644 Kboot/lds/bootloader_hi.ld delete mode 100644 Kboot/lds/bootloader_lo.ld delete mode 100644 Kboot/lds/kendryte.ld delete mode 100644 Kboot/lib/CMakeLists.txt delete mode 100644 Kboot/src/bootloader_hi/README.md delete mode 100644 Kboot/src/bootloader_hi/crt.S delete mode 100644 Kboot/src/bootloader_hi/fpioa.c delete mode 100644 Kboot/src/bootloader_hi/gpiohs.c delete mode 100644 Kboot/src/bootloader_hi/include/config.h delete mode 100644 Kboot/src/bootloader_hi/include/encoding.h delete mode 100644 Kboot/src/bootloader_hi/include/fpioa.h delete mode 100644 Kboot/src/bootloader_hi/include/gpiohs.h delete mode 100644 Kboot/src/bootloader_hi/include/platform.h delete mode 100644 Kboot/src/bootloader_hi/include/sha256.h delete mode 100644 Kboot/src/bootloader_hi/include/spi.h delete mode 100644 Kboot/src/bootloader_hi/include/sysctl.h delete mode 100644 Kboot/src/bootloader_hi/main.c delete mode 100644 Kboot/src/bootloader_hi/sha256.c delete mode 100644 Kboot/src/bootloader_lo/crt.S delete mode 100644 Kboot/src/bootloader_lo/include/encoding.h delete mode 100644 Kboot/src/bootloader_lo/include/platform.h delete mode 100644 Kboot/src/bootloader_lo/include/spi.h delete mode 100644 Kboot/src/bootloader_lo/include/sysctl.h delete mode 100644 Kboot/src/bootloader_lo/main.c diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..9950fb9 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "Kboot"] + path = Kboot + url = git@github.com:faisyl/Kboot.git diff --git a/Kboot b/Kboot new file mode 160000 index 0000000..7bae976 --- /dev/null +++ b/Kboot @@ -0,0 +1 @@ +Subproject commit 7bae9769a08892462bf8ffbeb61a27195a8d9495 diff --git a/Kboot/CMakeLists.txt b/Kboot/CMakeLists.txt deleted file mode 100644 index aacf504..0000000 --- a/Kboot/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -# DO NOT MODIFY THIS FILE, IT WILL BE OVERRIDE!!! - -# set this will supress some warnings -set(BUILDING_SDK "yes" CACHE INTERNAL "") - -# basic config -if (NOT PROJ) - get_filename_component(PROJ ${CMAKE_CURRENT_BINARY_DIR} DIRECTORY) - get_filename_component(PROJ ${PROJ} NAME) - string(REPLACE " " "_" PROJ ${PROJ}) - message(STATUS "PROJ not set, use ${PROJ} as PROJ. Also, you can set it manually. e.g. -DPROJ=hello_world") -else() - message("PROJ = ${PROJ}") -endif () -cmake_minimum_required(VERSION 3.0) - -include(./cmake/common.cmake) -project(${PROJ} C ASM) - -# config self use headers -include(./cmake/macros.internal.cmake) -header_directories(${SDK_ROOT}/lib) -header_directories(src/${PROJ}) -header_directories(kendryte-standalone-demo/${PROJ}) -# build library first -add_subdirectory(lib) - -# compile project -add_source_files(src/${PROJ}/*.c src/${PROJ}/*.s src/${PROJ}/*.S src/${PROJ}/*.cpp) -add_source_files(kendryte-standalone-demo/${PROJ}/*.c kendryte-standalone-demo/${PROJ}/*.s kendryte-standalone-demo/${PROJ}/*.S kendryte-standalone-demo/${PROJ}/*.cpp) -include(./cmake/executable.cmake) - diff --git a/Kboot/Kboot.md b/Kboot/Kboot.md deleted file mode 100644 index bc16e48..0000000 --- a/Kboot/Kboot.md +++ /dev/null @@ -1,182 +0,0 @@ -# Kboot - -**Kboot** is a small applications (< 8KB) which enables loading and executing applications from any K210 SPI Flash location. - -## Features - -* Load and execute K210 application stored at any location in SPI Flash. -* Application to be loaded is chosen from the list of available applications in **Kboot configuration sector**. -* Multiple criteria application validity check is performed when selecting the application. -* If no valid application is found **default application** is loaded and executed. -* The **interactive mode** can be enabled in which, based on the specific **Pin** state, the user can choose which application to load and execute from the list of found applications. -
- -## K210 Boot process when using **kboot** - -* After reset, the **1st part** (stage #0) of **Kboot** application is loaded by **K210 ROM** to SRAM address **`0x80000000`** and executed. -* SPI Flash driver is initialized in **XiP** mode. -* The **2nd part** (stage #1) of **Kboot** application is loaded to high SRAM address **`0x805E0000`** and the execution is continued fram that address. -* If allowed by configuration, **Boot Pin** state is checked and saved
If Boot Pin is activated (pulled to GND) **interactive mode** is enabled. -* **Configuration sector** is scanned for valid applications.
Following actions are performed: - * Configuration entry ID is checked - * Application Flash address is cheched for valid range - * Application size is checked for valid range - * If **Size** flag is set, application size is checked agains the acctual size written in application's _Flash block_. - * Application flags are saved - * Application _Flash block_ ***** is checked for valid format - * If **CRC32** flag is set, application's crc32 is calculated and checked - * If **SHA256** flag is set, application's SHA256 hash is calculated and checked -* If no valid application is found, the **backup** configuration sector is scanned. -* If all checks passes, the application is marked as **valid**. -* If **not in interactive mode**, configuration sector scan is terminated as soon as the first valid, flagged as **active** application is found and that application is loaded and executed. -* If in **interactive mode**, all configuration sector entries are scanned and the user is prompted to select which one to load and execute. -* If **no valid application** is found, the **default application** is loaded and executed -* If the **default application** fails the application test, the system is **halted** - -> ***** each application stored in SPI Flash has the following format: -> -> | Byte offset | Size | Name | Content | -> | ---: | ---: | :---: | :--- | -> | `0` | `1` | AES_FLAG | AES cipher flag, for use with **Kboot** must be `0` | -> | `1` | `4` | APP_SIZE | Application code size | -> | `5` | `APP_SIZE` | APP_CODE | Application code | -> | `APP_SIZE + 5` | `32` | SHA_HASH | Application SHA256 hash | -> -> All applications flashed with **ktool.py** or **kflash.py** have such format. - -
- -## K210 SPI Flash layout - -The following SPI Flash layout must be used when using **Kboot* - -| From | To | Length | Comment | -| ---: | ---: | ---: | :--- | -| `0x00000000` | `0x00000FFF` | 4K | 1st part of **Kboot** application, **stage #0** code | -| `0x00001000` | `0x00003FFF` | 12K | 2nd part of **Kboot** application, **stage #1** code | -| `0x00004000` | `0x00004FFF` | 4K | **main** boot configuration sector | -| `0x00005000` | `0x00005FFF` | 4K | **backup** boot configuration sector | -| `0x00006000` | `0x0000FFFF` | 40K | reserved, user data etc. | -| `0x00010000` | `DEF_APP_END` | --- | **default application** code | -| >`DEF_APP_END` | `FLASH_END` | --- | user area, application(s) code, file system(s), user data etc. | - -
- -## **Boot configuration** sector - -Boot configuration used by **Kboot** is stored in one SPI Flash sector (4KB) at fixed Flash address (`0x00004000`).
-One **backup** configuration sector is also used for security reasons, stored in one SPI Flash sector (4KB) at fixed Flash address (`0x00005000`).
- -The configuration sector consists of **`8`** _application entries_ occupying **`32`** bytes each.
-After the last application entry the **config flags** entry is placed, one 32bit value.
- -Configuration sector layout: - -| Offset | To | Length | Comment | -| ---: | ---: | ---: | :--- | -| `0x000` | `01F` | `32` | application entry #0 | -| `0x020` | `03F` | `32` | application entry #1 | -| `0x040` | `05F` | `32` | application entry #2 | -| `0x060` | `07F` | `32` | application entry #3 | -| `0x080` | `09F` | `32` | application entry #4 | -| `0x0A0` | `0BF` | `32` | application entry #5 | -| `0x0C0` | `0DF` | `32` | application entry #6 | -| `0x0E0` | `0FF` | `32` | application entry #7 | -| `0x100` | `103` | `4` | **config flags** | -| `0x104` | `11F` | `4` | reserved | -| `0x120` | `11F` | `4` | not used, user data | -
- -The format of each _application entry_ in configuration sector is as follows: - -| Offset | Length | Comment | -| ---: | ---: | :--- | -| `0` | `4` | Configuration entry **ID** (bits 4-31) + entry **flags** (bits 0-4) | -| `4` | `4` | Application address in SPI Flash | -| `8` | `4` | Application size in SPI Flash. This is the size of the application's **`.bin`** file | -| `12` | `4` | Application's CRC32 value (32bits) | -| `16` | `16` | Null terminated application name or description | - -_Notes:_
-Configuration entry **ID** must have a value of **`0x5AA5D0C0`** for entry to be recognized as valid.
-Application addres must be in range **`0x10000`** ~ **`0x800000`** ( 64KB ~ 8MB ).
-Application size must be in range **`0x4000`** ~ **`0x300000`** ( 16KB ~ 3MB ).
-Application CRC32 value is used only if **CRC32** flag is set.

- -If **config flags** at offset `0x100` in **configuration sector** is set to configuration entry **ID** (**`0x5AA5D0C0`**), **interractive mode** will be disabled, **boot Pin* will not be checked and nothing will be printed during the boot process. -Configuration entry **flags**: - -| Bit | Comment | -| :---: | :--- | -| `0` | **Active** flag, if set the application will be loaded and executed.
If multiple entries have **active** flag set, the first one will be loaded ad executed | -| `1` | **CRC32** flag, if set the application's CRC32 value will be calculated and compared with the value in the configuration entry | -| `2` | **AES256** flag, if set the application's AES256 hash value will be calculated and compared with the value stored in flash after the application code (`SHA_HASH`) | -| `3` | **Size** flag, if set the application size specified in configuration entry must match the application size present in application's _Flash block_ | - -**_Warning:_** all 32-bit values in the configuration sector entries must be written in **big-endian** format. - -
- -## Default application - -If in the boot process **no valid application** was found in the **configuration sector**, the **default application** is loaded and executed.
-**_The default application should try to check if loading it was **intended** or it was result of an error condition, in which case it should try to correct the issue._** - -
- -## Building the applications to be used with _Kboot_ - -Nothing special must be done to build the applications which are going to be used with **Kboot**.
-All applications built with Kendryte **Standalone SDK** or **FreeRTOS SDK** should run without issues.
- -The application can check if the **Kboot** system is used by reading the 2nd SPI Flash sector (at address **`0x1000`**).
-At offset `0x09` the `Kboot` **id string** is positioned: **`Kboot_v1.4.1`** (version mumbers may be different).
- -``` -[00001000] 00 B0 1F 00 00 6F 00 40 01 4B 62 6F 6F 74 5F 76 31 2E 34 2E 31 00 00 00 00 19 71 86 FC A2 F8 A6 -[00001020] F4 CA F0 CE EC D2 E8 D6 E4 DA E0 5E FC 62 F8 66 F4 6A F0 6E EC F3 27 40 F1 81 27 17 27 00 00 23 -``` - -_See the note about sector data!_ - -

- -## Usage - -Flashing the application(s) to SPI Flash and manipulating the boot **configuration sector** should be performed from the user application.
-Accessing SPI flash from K210 application is quite easy and reliable. - - - -### Example - -**Application firmware update** - -* The condition to update the firmware is detected by the application -* Load the **boot configuration** sector, check its integrity and check the flash address and size of the currently running application -* Flash the new firmware to the **not used** SPI Flash area. The new firmware can be downloaded from remote server using WiFi or GSM, loaded from SD Card, etc ...
Use the **application block** format described above.
The application can be flashed **without** SHA256 hash, in that case do not set the **`SHA256`** flag. -* Calculate new firmware's CRC32 and/or SHA256 hash if needed. -* Flash the current **main** boot configuration sector to the **backup** boot configuration sector and check it.
It will be used by **Kboot** in case the **main** boot configuration sector which we are going to write is corrupted. -* Update (add or change entry) in the boot configuration sector with the new firmware information, set the new firmware as active and the old firmware as inactive and flash the configuration sector. -* Reset (reboot) the system to start the new firmware. - - -### Important Notes - -When reading sectors written with **ktool.p<** or **kflash.py** from SPI Flash in **normal** mode (not using **XiP** mode), the sector data may look corrupted.
-The reason is that all sector data are written with **swapped** 32-bit values (32-bit **big endian** format is used).
-To correct this, you should **swap endianess** of all 32-bit values in the sector, something like this:.
- -``` -uint8_t buf4[4]; -for (int k=0; k<4096; k+=4) { - buf4[0] = sector[k+0]; - buf4[1] = sector[k+1]; - buf4[2] = sector[k+2]; - buf4[3] = sector[k+3]; - sector[k+0] = buf4[3]; - sector[k+1] = buf4[2]; - sector[k+2] = buf4[1]; - sector[k+3] = buf4[0]; -} -``` diff --git a/Kboot/README.md b/Kboot/README.md deleted file mode 100644 index 27862bf..0000000 --- a/Kboot/README.md +++ /dev/null @@ -1,204 +0,0 @@ -# Kboot - -**Kboot** is a small applications which enables loading and executing applications from any K210 SPI Flash location. - -It can be used to implement firmware upgrade (OTA) or to load different (multiple) applications based on some criteria. - -Interactive mode is also provided which enables the user to select which application to load and execute from the list of stored applications. - ---- -> More details about **Kboot** are available in the [**Kboot.md**](https://github.com/loboris/Kboot/blob/master/Kboot.md). ---- - -
- -## How to build - -Clone the repository or download and unpack the repository zip file. - -**The repository contains all the tools and sources needed to build `Kboot`.** - -The same build prerequisites must be satisfied as for building any other K210 application.
- -Default application (**`config.bin`**, which runs if no configured aplications are found), default configuration sector (**`config.bin`**) and 3 example applications are provided.
- -Example applications:
-**MicroPython.bin**, built with **_FreeRTOS SDK_** is expected to be found at Flash address **`0x00080000`** (512 KB),
-**dvp_ov.bin**, **_Standalone SDK_** example, is expected to be found at Flash address **`0x00280000`** (2.5 MB)
-**maixpy.bin**, built with **_Standalone SDK_**, is expected to be found at Flash address **`0x00280000`** (2.5 MB)
- -You can flash the default application executting: - -```console -./ktool.py -p /dev/ttyUSB0 -a 65536 -b 2000000 -t default.bin -``` - -You can flash one of example aplications executing: - -```console -./ktool.py -p /dev/ttyUSB0 -a 524288 -b 2000000 -t MicroPython.bin -./ktool.py -p /dev/ttyUSB0 -a 2621440 -b 2000000 -t dvp_ov.bin -./ktool.py -p /dev/ttyUSB0 -a 2621440 -b 2000000 -t maixpy.bin -``` - -### Build from source - -* Change the working directory to the **`build`** directory. -* A simple build script **`BUILD.sh`** is provided which builds the **`Kboot`** application. -* Simply execute `BUILD.sh` -* **`kboot.kfpkg`** package will be created which includes `bootloader_lo.bin` and `bootloader_hi.bin` binaries and the default configuration. - -### Flash to K210 board - -**`kboot.kfpkg`** can be flashed to the K210 using the included [**`ktool.py`**](https://github.com/loboris/ktool).
-**_Note:_** Do not use standard **`kflash.py`**, **kboot** binaries requires flashing **4KB aligned blocks**, which is not supported by standard `kflash.py`. - -
- -### Examples - -Build the **`Kboot`** package: - -```console -boris@UbuntuMate:/home/kboot/build$ ./BUILD.sh - - =========================== - === Building bootloader === - =========================== - -=== Running 'cmake' -=== Running 'make' -Scanning dependencies of target kendryte -[ 25%] Linking C static library libkendryte.a -[ 25%] Built target kendryte -Scanning dependencies of target bootloader_lo -[ 75%] Building C object CMakeFiles/bootloader_lo.dir/src/bootloader_lo/main.c.obj -[ 75%] Building ASM object CMakeFiles/bootloader_lo.dir/src/bootloader_lo/crt.S.obj -[100%] Linking C executable bootloader_lo -Generating .bin file ... -[100%] Built target bootloader_lo - -=== Finished ---------------------------------------------------- - text data bss dec hex filename - 496 112 8 616 268 bootloader_lo ---------------------------------------------------- - -=== Running 'cmake' -=== Running 'make' -Scanning dependencies of target kendryte -[ 14%] Linking C static library libkendryte.a -[ 14%] Built target kendryte -Scanning dependencies of target bootloader_hi -[ 28%] Building ASM object CMakeFiles/bootloader_hi.dir/src/bootloader_hi/crt.S.obj -[ 71%] Building C object CMakeFiles/bootloader_hi.dir/src/bootloader_hi/main.c.obj -[ 71%] Building C object CMakeFiles/bootloader_hi.dir/src/bootloader_hi/fpioa.c.obj -[ 71%] Building C object CMakeFiles/bootloader_hi.dir/src/bootloader_hi/gpiohs.c.obj -[ 85%] Building C object CMakeFiles/bootloader_hi.dir/src/bootloader_hi/sha256.c.obj -[100%] Linking C executable bootloader_hi -Generating .bin file ... -[100%] Built target bootloader_hi - -=== Finished --------------------------------------------------- - text data bss dec hex filename - 6848 1264 88 8200 2008 bootloader_hi --------------------------------------------------- - -=== Creating 'kboot.kfpkg' - --------------------------------------------------------------------- -To flash the kboot package to K210 run: -./ktool.py -p /dev/ttyUSB0 -b 2000000 -t kboot.kfpkg - -To flash default application run: -./ktool.py -p /dev/ttyUSB0 -a 65536 -b 2000000 -t default.bin - -Default config can run applications from 512K or 2.5M flash address -Some applications are provided for testing: - -To flash MicroPython (FreeRTOS SDK) at 512K, run: -./ktool.py -p /dev/ttyUSB0 -a 524288 -b 2000000 -t MicroPython.bin -To flash dvp_ov (Standalone SDK) at 2.5M, run: -./ktool.py -p /dev/ttyUSB0 -a 2621440 -b 2000000 -t dvp_ov.bin -To flash maixpy (Standalone SDK) at 2.5M, run: -./ktool.py -p /dev/ttyUSB0 -a 2621440 -b 2000000 -t maixpy.bin - -If no app is found, default app will be run which blinks the LED(s). --------------------------------------------------------------------- - -boris@UbuntuMate:/home/kboot/build$ -``` - -Flash **`Kboot`** package to K210 board: - -```console -boris@UbuntuMate:/home/kboot/build$ ./ktool.py -p /dev/ttyUSB0 -b 2000000 -t kboot.kfpkg -[INFO] COM Port Selected Manually: /dev/ttyUSB0 -[INFO] Default baudrate is 115200 , later it may be changed to the value you set. -[INFO] Trying to Enter K210 ROM ISP Mode... -. -[INFO] Automatically detected dan/bit/trainer - -[INFO] ROM ISP detected, loading 2nd stage ISP -[INFO] ISP loaded in 0.921s -[INFO] Starting 2nd stage ISP at 0x805e0000 -[INFO] Wait For 0.1 second for ISP to Boot -[INFO] 2nd stage ISP ok -[INFO] Selected Baudrate: 2000000 -[INFO] Baudrate changed, greeting with ISP again ... -[INFO] 2nd stage ISP ok -[INFO] Initialize K210 SPI Flash -[INFO] Flash initialized successfully -[INFO] Flash ID: 0xC86018, unique ID: 384130323209302A, size: 16 MB -[INFO] Extracting KFPKG ... -[INFO] Writing bootloader_lo.bin to Flash address 0x00000000 -[INFO] Flashing firmware block with SHA suffix -Programming BIN: |=========================================================================================================| 100.0% -[INFO] Flashed 645 B [1 chunks of 4096B] (00000000~00000FFF) in 0.137s -[INFO] Writing bootloader_hi.bin to Flash address 0x00001000 -[INFO] Flashing firmware block with SHA suffix -Programming BIN: |=========================================================================================================| 100.0% -[INFO] Flashed 8149 B [2 chunks of 4096B] (00001000~00002FFF) in 0.255s -[INFO] Writing config.bin to Flash address 0x00004000 -Programming DATA: |=========================================================================================================| 100.0% -[INFO] Flashed 4096 B [1 chunks of 4096B] (00004000~00004FFF) in 0.132s -[INFO] Writing config.bin to Flash address 0x00005000 -Programming DATA: |=========================================================================================================| 100.0% -[INFO] Flashed 4096 B [1 chunks of 4096B] (00005000~00005FFF) in 0.129s -[INFO] Rebooting... - ---- forcing DTR inactive ---- forcing RTS inactive ---- Miniterm on /dev/ttyUSB0 115200,8,N,1 --- ---- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H --- - -K210 bootloader by LoBo v.1.4.1 - -* Find applications in MAIN parameters - 0: ' dvp_ov example', @ 0x00280000, size=77248, app_size=1679808, App ok, NOT ACTIVE - 1: ' MicroPython', @ 0x00080000, size=1744896, app_size=1789952, App ok, ACTIVE - 2: ' maixpy', @ 0x00280000, size=1681856, app_size=1679808, App ok, NOT ACTIVE - -Select the application number to load [ 0, 1, 2, d=default ] ? 1 - -* Loading app from flash at 0x00080000 (1789952 B) -* Starting at 0x80000000 ... - -M (37678) [K210_MAIN]: Default flash configuration set - -RISC-V Kendryte --------------------------------------------- - _ _ _____ _ ______ ___ ___ ______ _ _ -( ) / ) (___ ) ( ) ( __ ) ( \ / ) ( __ ) ( ) ( ) -| |_/ / ___| | | | | | | | | |\ \ /| | | |__| | \ \_/ / -| _ ) ( ____) | | | | | |**| | \_/ | | | ____) \ / -| | \ \ | |___ | | | |__| | | | | | | | | | -(_) \_) (_____) (_) (______) (_) (_) (_) (_) -------------------------------------------------------------- -MicroPython-FreeRTOS by LoBo v1.11.12 (two MPY tasks) ------------------------------------------------------ - -MicroPython 1.11.12 (1abe503-dirty) built on 2020-01-02; Sipeed_board with Kendryte-K210 -Type "help()" for more information. ->>> -``` diff --git a/Kboot/cmake/CMakeLists.txt b/Kboot/cmake/CMakeLists.txt deleted file mode 100644 index 64f2708..0000000 --- a/Kboot/cmake/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -### This file is used for build library standalone. - -# set this will supress some warnings -set(BUILDING_SDK "yes" CACHE INTERNAL "") - -# basic config -cmake_minimum_required(VERSION 3.0) -include(./common.cmake) -project(kendryte) - -# config self use headers -include(./macros.internal.cmake) -header_directories(${SDK_ROOT}/lib) - -# include lib make file -include(../lib/CMakeLists.txt) - -# find headers files to INSTALL -file(GLOB_RECURSE LIB_HEADERS - "../lib/*.h" - "../lib/*.hpp" - ) -set_target_properties(kendryte PROPERTIES PUBLIC_HEADER "${LIB_HEADERS}") - -# copy .a file and headers -install(TARGETS kendryte - EXPORT kendryte - ARCHIVE - DESTINATION ${CMAKE_BINARY_DIR}/archive - PUBLIC_HEADER DESTINATION ${CMAKE_BINARY_DIR}/archive/include - ) - -# copy utils files -install(DIRECTORY - ../lds - ../utils - ../cmake - DESTINATION ${CMAKE_BINARY_DIR}/archive - PATTERN "*internal*" EXCLUDE - PATTERN "CMakeLists.txt" EXCLUDE - ) - -# show information -include(./dump-config.cmake) diff --git a/Kboot/cmake/README.md b/Kboot/cmake/README.md deleted file mode 100644 index 5e5bc8b..0000000 --- a/Kboot/cmake/README.md +++ /dev/null @@ -1,3 +0,0 @@ -prepend `common.cmake` before - -append `executable.cmake` after diff --git a/Kboot/cmake/common.cmake b/Kboot/cmake/common.cmake deleted file mode 100644 index a4eec83..0000000 --- a/Kboot/cmake/common.cmake +++ /dev/null @@ -1,43 +0,0 @@ -cmake_minimum_required(VERSION 3.0) - -include(${CMAKE_CURRENT_LIST_DIR}/macros.cmake) - -global_set(CMAKE_C_COMPILER_WORKS 1) -global_set(CMAKE_CXX_COMPILER_WORKS 1) - -global_set(CMAKE_SYSTEM_NAME "Generic") -if (NOT CMAKE_BUILD_TYPE) - global_set(CMAKE_BUILD_TYPE Release) -else () - if ((NOT CMAKE_BUILD_TYPE STREQUAL "Debug") AND (NOT CMAKE_BUILD_TYPE STREQUAL "Release")) - message(FATAL_ERROR "CMAKE_BUILD_TYPE must either be Debug or Release instead of ${CMAKE_BUILD_TYPE}") - endif () -endif () - -if (NOT NO_BOOT_LOGGING) - global_set(BOOT_LOGGING -DLOGGING_ENABLED) -endif () - -# - Debug & Release -IF (CMAKE_BUILD_TYPE STREQUAL Debug) - add_definitions(-DDEBUG=1) -ENDIF () - -# definitions in macros -add_definitions(${BOOT_LOGGING} -DCONFIG_LOG_LEVEL=LOG_NONE -DCONFIG_LOG_ENABLE -DCONFIG_LOG_COLORS -DLOG_KERNEL -D__riscv64 -DLV_CONF_INCLUDE_SIMPLE) - -# xtl options -add_definitions(-DTCB_SPAN_NO_EXCEPTIONS -DTCB_SPAN_NO_CONTRACT_CHECKING) -# nncase options -add_definitions(-DNNCASE_TARGET=k210) - -if (NOT SDK_ROOT) - get_filename_component(_SDK_ROOT ${CMAKE_CURRENT_LIST_DIR} DIRECTORY) - global_set(SDK_ROOT ${_SDK_ROOT}) -endif () - -include(${CMAKE_CURRENT_LIST_DIR}/toolchain.cmake) - -include(${CMAKE_CURRENT_LIST_DIR}/compile-flags.cmake) - -include(${CMAKE_CURRENT_LIST_DIR}/fix-9985.cmake) diff --git a/Kboot/cmake/compile-flags.cmake b/Kboot/cmake/compile-flags.cmake deleted file mode 100644 index 83a6776..0000000 --- a/Kboot/cmake/compile-flags.cmake +++ /dev/null @@ -1,67 +0,0 @@ -add_compile_flags(LD - -nostartfiles - -static - -Wl,--gc-sections - -Wl,-static - -Wl,--start-group - -Wl,--whole-archive - -Wl,--no-whole-archive - -Wl,--end-group - -Wl,-EL - -Wl,--no-relax - -T ${SDK_ROOT}/lds/kendryte.ld - ) - -# C Flags Settings -add_compile_flags(BOTH - -mcmodel=medany - -mabi=lp64f - -march=rv64imafdc - -fno-common - -ffunction-sections - -fdata-sections - -fstrict-volatile-bitfields - -fno-zero-initialized-in-bss - -ffast-math - -fno-math-errno - -fsingle-precision-constant - -fPIC - -O0 - -ggdb - ) - -add_compile_flags(C -std=gnu11 -Wno-pointer-to-int-cast) -add_compile_flags(CXX -std=gnu++17) - -if (BUILDING_SDK) - add_compile_flags(BOTH - -Wall - -Werror=all - -Wno-error=unused-function - -Wno-error=unused-but-set-variable - -Wno-error=unused-variable - -Wno-error=deprecated-declarations - -Wno-multichar - -Wextra - -Werror=frame-larger-than=32768 - -Wno-unused-parameter - -Wno-sign-compare - -Wno-error=missing-braces - -Wno-error=return-type - -Wno-error=pointer-sign - -Wno-missing-braces - -Wno-strict-aliasing - -Wno-implicit-fallthrough - -Wno-missing-field-initializers - -Wno-int-to-pointer-cast - -Wno-error=comment - -Wno-error=logical-not-parentheses - -Wno-error=duplicate-decl-specifier - -Wno-error=parentheses - ) - - add_compile_flags(C -Wno-old-style-declaration) -else () - add_compile_flags(BOTH -L${SDK_ROOT}/include/) -endif () - diff --git a/Kboot/cmake/dump-config.cmake b/Kboot/cmake/dump-config.cmake deleted file mode 100644 index 8531f6c..0000000 --- a/Kboot/cmake/dump-config.cmake +++ /dev/null @@ -1,22 +0,0 @@ -message("") -message("Project: ${PROJECT_NAME}") -message(" LIST_FILE=${CMAKE_PARENT_LIST_FILE}") -message(" TOOLCHAIN=${TOOLCHAIN}") -message(" KENDRYTE_IDE=${KENDRYTE_IDE}") -message(" BUILDING_SDK=${BUILDING_SDK}") -message("") -message(" CMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}") -message(" CMAKE_C_COMPILER=${CMAKE_C_COMPILER}") -message(" CMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}") -message(" CMAKE_LINKER=${CMAKE_LINKER}") -message(" CMAKE_OBJCOPY=${CMAKE_OBJCOPY}") -message(" CMAKE_OBJDUMP=${CMAKE_OBJDUMP}") -message(" CMAKE_MAKE_PROGRAM=${CMAKE_MAKE_PROGRAM}") -message("") -message(" CMAKE_C_FLAGS=${CMAKE_C_FLAGS}") -message(" CMAKE_CXX_FLAGS=${CMAKE_CXX_FLAGS}") -message(" LDFLAGS=${LDFLAGS}") -message(" CMAKE_BINARY_DIR=${CMAKE_BINARY_DIR}") -message("Makefile created.") -message("") -message("") diff --git a/Kboot/cmake/executable.cmake b/Kboot/cmake/executable.cmake deleted file mode 100644 index 522e70b..0000000 --- a/Kboot/cmake/executable.cmake +++ /dev/null @@ -1,45 +0,0 @@ -if (NOT BUILDING_SDK) - if(EXISTS ${SDK_ROOT}/libkendryte.a) - add_library(kendryte STATIC IMPORTED) - set_property(TARGET kendryte PROPERTY IMPORTED_LOCATION ${SDK_ROOT}/libkendryte.a) - include_directories(${SDK_ROOT}/include/) - else() - header_directories(${SDK_ROOT}/lib) - add_subdirectory(${SDK_ROOT}/lib) - endif() -endif () - -removeDuplicateSubstring(${CMAKE_C_FLAGS} CMAKE_C_FLAGS) -removeDuplicateSubstring(${CMAKE_CXX_FLAGS} CMAKE_CXX_FLAGS) - -message("SOURCE_FILES=${SOURCE_FILES}") -add_executable(${PROJECT_NAME} ${SOURCE_FILES}) - - -set_target_properties(${PROJECT_NAME} PROPERTIES LINKER_LANGUAGE C) - -target_link_libraries(${PROJECT_NAME} - -Wl,--start-group - gcc m c - -Wl,--whole-archive - kendryte - -Wl,--no-whole-archive - -Wl,--end-group - ) - -if (EXISTS ${SDK_ROOT}/src/${PROJ}/project.cmake) - include(${SDK_ROOT}/src/${PROJ}/project.cmake) -endif () - -IF(SUFFIX) - SET_TARGET_PROPERTIES(${PROJECT_NAME} PROPERTIES SUFFIX ${SUFFIX}) -ENDIF() - -# Build target -add_custom_command(TARGET ${PROJECT_NAME} POST_BUILD - COMMAND ${CMAKE_OBJCOPY} --output-format=binary ${CMAKE_BINARY_DIR}/${PROJECT_NAME}${SUFFIX} ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.bin - DEPENDS ${PROJECT_NAME} - COMMENT "Generating .bin file ...") - -# show information -include(${CMAKE_CURRENT_LIST_DIR}/dump-config.cmake) diff --git a/Kboot/cmake/fix-9985.cmake b/Kboot/cmake/fix-9985.cmake deleted file mode 100644 index 4402bd3..0000000 --- a/Kboot/cmake/fix-9985.cmake +++ /dev/null @@ -1,3 +0,0 @@ -### http://www.cmake.org/Bug/view.php?id=9985 -string(REPLACE "-rdynamic" "" CMAKE_SHARED_LIBRARY_LINK_C_FLAGS "${CMAKE_SHARED_LIBRARY_LINK_C_FLAGS}") -string(REPLACE "-rdynamic" "" CMAKE_SHARED_LIBRARY_LINK_CXX_FLAGS "${CMAKE_SHARED_LIBRARY_LINK_CXX_FLAGS}") diff --git a/Kboot/cmake/ide.cmake b/Kboot/cmake/ide.cmake deleted file mode 100644 index 0c3db5f..0000000 --- a/Kboot/cmake/ide.cmake +++ /dev/null @@ -1,7 +0,0 @@ -FILE(GLOB_RECURSE ASSEMBLY_FILES - "${CMAKE_CURRENT_LIST_DIR}/*.s" - "${CMAKE_CURRENT_LIST_DIR}/*.S" -) - -SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C) -SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64") diff --git a/Kboot/cmake/macros.cmake b/Kboot/cmake/macros.cmake deleted file mode 100644 index ab75e24..0000000 --- a/Kboot/cmake/macros.cmake +++ /dev/null @@ -1,72 +0,0 @@ -macro(global_set Name Value) - # message("set ${Name} to " ${ARGN}) - set(${Name} "${Value}" CACHE STRING "NoDesc" FORCE) -endmacro() - -macro(condition_set Name Value) - if (NOT ${Name}) - global_set(${Name} ${Value}) - else () - # message("exists ${Name} is " ${ARGN}) - endif () -endmacro() - - -set(SOURCE_FILES "" CACHE STRING "Source Files" FORCE) -macro(add_source_files) - # message(" + add_source_files ${ARGN}") - file(GLOB_RECURSE newlist ${ARGN}) - - foreach (filepath ${newlist}) - string(FIND ${filepath} ${CMAKE_BINARY_DIR} found) - if (NOT found EQUAL 0) - set(SOURCE_FILES ${SOURCE_FILES} ${filepath} CACHE STRING "Source Files" FORCE) - endif () - endforeach () -endmacro() - -function(JOIN VALUES GLUE OUTPUT) - string(REGEX REPLACE "([^\\]|^);" "\\1${GLUE}" _TMP_STR "${VALUES}") - string(REGEX REPLACE "[\\](.)" "\\1" _TMP_STR "${_TMP_STR}") #fixes escaping - set(${OUTPUT} "${_TMP_STR}" PARENT_SCOPE) -endfunction() - -global_set(LDFLAGS "") -global_set(CMAKE_EXE_LINKER_FLAGS "") -global_set(CMAKE_SHARED_LINKER_FLAGS "") -global_set(CMAKE_MODULE_LINKER_FLAGS "") - -function(removeDuplicateSubstring stringIn stringOut) - separate_arguments(stringIn) - list(REMOVE_DUPLICATES stringIn) - string(REPLACE ";" " " stringIn "${stringIn}") - set(${stringOut} "${stringIn}" PARENT_SCOPE) -endfunction() - -macro(add_compile_flags WHERE) - JOIN("${ARGN}" " " STRING_ARGS) - if (${WHERE} STREQUAL C) - global_set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${STRING_ARGS}") - - elseif (${WHERE} STREQUAL CXX) - global_set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${STRING_ARGS}") - - elseif (${WHERE} STREQUAL LD) - global_set(LDFLAGS "${LDFLAGS} ${STRING_ARGS}") - global_set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${STRING_ARGS}") - global_set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${STRING_ARGS}") - global_set(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${STRING_ARGS}") - - elseif (${WHERE} STREQUAL BOTH) - add_compile_flags(C ${ARGN}) - add_compile_flags(CXX ${ARGN}) - - elseif (${WHERE} STREQUAL ALL) - add_compile_flags(C ${ARGN}) - add_compile_flags(CXX ${ARGN}) - add_compile_flags(LD ${ARGN}) - - else () - message(FATAL_ERROR "add_compile_flags - only support: C, CXX, BOTH, LD, ALL") - endif () -endmacro() diff --git a/Kboot/cmake/macros.internal.cmake b/Kboot/cmake/macros.internal.cmake deleted file mode 100644 index a38b56d..0000000 --- a/Kboot/cmake/macros.internal.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# Add lib headers -macro(header_directories parent) - file(GLOB_RECURSE newList ${parent}/*.h) - set(dir_list "") - foreach (file_path ${newList}) - get_filename_component(dir_path ${file_path} DIRECTORY) - set(dir_list ${dir_list} ${dir_path}) - endforeach () - list(REMOVE_DUPLICATES dir_list) - - include_directories(${dir_list}) -endmacro() \ No newline at end of file diff --git a/Kboot/cmake/toolchain.cmake b/Kboot/cmake/toolchain.cmake deleted file mode 100644 index ea10e46..0000000 --- a/Kboot/cmake/toolchain.cmake +++ /dev/null @@ -1,51 +0,0 @@ -if (WIN32) - set(EXT ".exe") -else () - set(EXT "") -endif () - -message(STATUS "Check for RISCV toolchain ...") -if(NOT TOOLCHAIN) - find_path(_TOOLCHAIN riscv64-unknown-elf-gcc${EXT}) - global_set(TOOLCHAIN "${_TOOLCHAIN}") -elseif(NOT "${TOOLCHAIN}" MATCHES "/$") - global_set(TOOLCHAIN "${TOOLCHAIN}") -endif() - -if (NOT TOOLCHAIN) - message(FATAL_ERROR "TOOLCHAIN must be set, to absolute path of kendryte-toolchain dist/bin folder.") -endif () - -message(STATUS "Using ${TOOLCHAIN} RISCV toolchain") - -global_set(CMAKE_C_COMPILER "${TOOLCHAIN}/riscv64-unknown-elf-gcc${EXT}") -global_set(CMAKE_CXX_COMPILER "${TOOLCHAIN}/riscv64-unknown-elf-g++${EXT}") -global_set(CMAKE_LINKER "${TOOLCHAIN}/riscv64-unknown-elf-ld${EXT}") -global_set(CMAKE_AR "${TOOLCHAIN}/riscv64-unknown-elf-ar${EXT}") -global_set(CMAKE_OBJCOPY "${TOOLCHAIN}/riscv64-unknown-elf-objcopy${EXT}") -global_set(CMAKE_SIZE "${TOOLCHAIN}/riscv64-unknown-elf-size${EXT}") -global_set(CMAKE_OBJDUMP "${TOOLCHAIN}/riscv64-unknown-elf-objdump${EXT}") -if (WIN32) - if(EXISTS "${TOOLCHAIN}/make${EXT}") - global_set(CMAKE_MAKE_PROGRAM "${TOOLCHAIN}/make${EXT}") - else() - global_set(CMAKE_MAKE_PROGRAM "${TOOLCHAIN}/mingw32-make${EXT}") - endif() -endif () - -execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crt0.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRT0_OBJ) -execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crtbegin.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTBEGIN_OBJ) -execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crtend.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTEND_OBJ) -execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crti.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTI_OBJ) -execute_process(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crtn.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTN_OBJ) - -global_set(CMAKE_C_LINK_EXECUTABLE - " \"${CRTI_OBJ}\" \"${CRTBEGIN_OBJ}\" \"${CRTEND_OBJ}\" \"${CRTN_OBJ}\" -o ") - -global_set(CMAKE_CXX_LINK_EXECUTABLE - " \"${CRTI_OBJ}\" \"${CRTBEGIN_OBJ}\" \"${CRTEND_OBJ}\" \"${CRTN_OBJ}\" -o ") - -get_filename_component(_BIN_DIR "${CMAKE_C_COMPILER}" DIRECTORY) -if (NOT "${TOOLCHAIN}" STREQUAL "${_BIN_DIR}") - message(FATAL_ERROR "CMAKE_C_COMPILER is not in kendryte-toolchain dist/bin folder.") -endif () diff --git a/Kboot/lds/bootloader_hi.ld b/Kboot/lds/bootloader_hi.ld deleted file mode 100644 index fc99e70..0000000 --- a/Kboot/lds/bootloader_hi.ld +++ /dev/null @@ -1,263 +0,0 @@ -/* - * The MEMORY command describes the location and size of blocks of memory - * in the target. You can use it to describe which memory regions may be - * used by the linker, and which memory regions it must avoid. - */ -MEMORY -{ - /* - * Memory with CPU cache. - * 64K CPU SRAM - */ - ram (wxari) : ORIGIN = 0x805E0000, LENGTH = 0x00008000 - /* - * Memory without CPU cache - * 64K CPU SRAM - */ - ram_nocache (wxari) : ORIGIN = 0x405E0000, LENGTH = 0x00008000 -} - -PROVIDE( _rom_start = ORIGIN(rom) ); -PROVIDE( _rom_end = ORIGIN(rom) + LENGTH(rom) ); -PROVIDE( _ram_start = ORIGIN(ram) ); -PROVIDE( _ram_end = ORIGIN(ram) + LENGTH(ram) ); -PROVIDE( _io_start = ORIGIN(ram_nocache) ); -PROVIDE( _io_end = _io_start + LENGTH(ram_nocache) ); - - -/* - * The OUTPUT_ARCH command specifies the machine architecture where the - * argument is one of the names used in the Kendryte library. - */ -OUTPUT_ARCH( "riscv" ) - -/* - * The ENTRY command specifies the entry point (ie. first instruction to - * execute). The symbol _start is defined in crt0.S - */ -ENTRY(_start) - -/* - * The GROUP command is special since the listed archives will be - * searched repeatedly until there are no new undefined references. We - * need this since -lc depends on -lgloss and -lgloss depends on -lc. I - * thought gcc would automatically include -lgcc when needed, but - * in this file includes it explicitly here and I was seeing link errors - * without it. - */ -/* GROUP( -lc -lgloss -lgcc ) */ - -/* - * The linker only pays attention to the PHDRS command when generating - * an ELF output file. In other cases, the linker will simply ignore PHDRS. - */ -PHDRS -{ - ram_ro PT_LOAD; - ram_init PT_LOAD; - ram PT_NULL; -} - -/* - * This is where we specify how the input sections map to output - * sections. - */ -SECTIONS -{ - /* Program code segment, also known as a text segment */ - .text : - { - PROVIDE( _text = ABSOLUTE(.) ); - /* Initialization code segment */ - KEEP( *(.text.start) ) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - /* Normal code segment */ - *(.text .text.*) - *(.gnu.linkonce.t.*) - - . = ALIGN(8); - PROVIDE( _etext = ABSOLUTE(.) ); - } >ram AT>ram :ram_ro - - /* Read-only data segment */ - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >ram AT>ram :ram_ro - - . = ALIGN(8); - - /* Exception handling */ - .eh_frame : - { - KEEP (*(.eh_frame)) *(.eh_frame.*) - . = ALIGN(8); - } >ram AT>ram :ram_ro - .gnu_extab : { *(.gnu_extab) } >ram AT>ram :ram_ro - .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } >ram AT>ram :ram_ro - .exception_ranges : { *(.exception_ranges .exception_ranges*) } >ram AT>ram :ram_ro - - /* Init array and fini array */ - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >ram AT>ram :ram_ro - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - *(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors) - PROVIDE_HIDDEN (__init_array_end = .); - } >ram AT>ram :ram_ro - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >ram AT>ram :ram_ro - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >ram AT>ram :ram_ro - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >ram AT>ram :ram_ro - - . = ALIGN(8); - - .lalign : - { - . = ALIGN(8); - PROVIDE( _data_lma = . ); - } >ram AT>ram :ram_ro - - .dalign : - { - . = ALIGN(8); - PROVIDE( _data = . ); - } >ram AT>ram :ram_init - - . = ALIGN(8); - - /* .data, .sdata and .srodata segment */ - .data : - { - /* Writable data segment (.data segment) */ - *(.data .data.*) - *(.gnu.linkonce.d.*) - /* Have _gp point to middle of sdata/sbss to maximize displacement range */ - . = ALIGN(8); - PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800); - /* Writable small data segment (.sdata segment) */ - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - /* Read-only small data segment (.srodata segment) */ - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - /* Align _edata to cache line size */ - . = ALIGN(64); - PROVIDE( _edata = ABSOLUTE(.) ); - } >ram AT>ram :ram_init - - /* .bss and .sbss segment */ - .bss : - { - PROVIDE( _bss = ABSOLUTE(.) ); - /* Writable uninitialized small data segment (.sbss segment)*/ - *(.sbss .sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - /* Uninitialized writeable data section (.bss segment)*/ - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(8); - PROVIDE( _ebss = ABSOLUTE(.) ); - } >ram AT>ram :ram - - PROVIDE( _tls_data = ABSOLUTE(.) ); - /* - * Thread Local Storage (TLS) are per-thread global variables. - * Compilers such as GCC provide a __thread keyword to mark global - * variables as per-thread. Support is required in the program loader - * and thread creator. - */ - - /* Thread-local data segment, .tdata (initialized tls). */ - .tdata : - { - KEEP( *(.tdata.begin) ) - *(.tdata .tdata.*) - *(.gnu.linkonce.td.*) - KEEP( *(.tdata.end) ) - } >ram AT>ram :ram - - /* Thread-local bss segment, .tbss (zero-initialized tls). */ - .tbss : - { - *(.tbss .tbss.*) - *(.gnu.linkonce.tb.*) - KEEP( *(.tbss.end) ) - } >ram AT>ram :ram - - /* - * End of uninitalized data segement - * - * Actually the stack needs 16B alignment, and it won't hurt to also slightly - * increase the alignment to 32 or even 64 (cache line size). - * - * Align _heap_start to cache line size - */ - . = ALIGN(64); - PROVIDE( _end = ABSOLUTE(.) ); - /* Leave 2 holes for stack & TLS, the size can set in kconfig */ - - PROVIDE( _heap_start = ABSOLUTE(.) ); - /* - PROVIDE( _tp0 = (_end + 63) & (-64) ); - PROVIDE( _tp1 = _tp0 + _stack_size ); - PROVIDE( _sp0 = _tp0 + _stack_size ); - PROVIDE( _sp1 = _tp1 + _stack_size ); - */ - - /* Heap end is at the end of memory, the memory size can set in kconfig */ - PROVIDE( _heap_end = _ram_end ); -} - diff --git a/Kboot/lds/bootloader_lo.ld b/Kboot/lds/bootloader_lo.ld deleted file mode 100644 index bf2c5c4..0000000 --- a/Kboot/lds/bootloader_lo.ld +++ /dev/null @@ -1,265 +0,0 @@ -/* - * The MEMORY command describes the location and size of blocks of memory - * in the target. You can use it to describe which memory regions may be - * used by the linker, and which memory regions it must avoid. - */ -MEMORY -{ - /* - * Memory with CPU cache. - * 64K CPU SRAM - */ - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x00008000 - /* - * Memory without CPU cache - * 64K CPU SRAM - */ - ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 0x00008000 -} - -PROVIDE( _rom_start = ORIGIN(rom) ); -PROVIDE( _rom_end = ORIGIN(rom) + LENGTH(rom) ); -PROVIDE( _ram_start = ORIGIN(ram) ); -PROVIDE( _ram_end = ORIGIN(ram) + LENGTH(ram) ); -PROVIDE( _io_start = ORIGIN(ram_nocache) ); -PROVIDE( _io_end = _io_start + LENGTH(ram_nocache) ); -PROVIDE( _stack_size = 1 << 15 ); -PROVIDE( _stack_start = 0x80540000 ); - - -/* - * The OUTPUT_ARCH command specifies the machine architecture where the - * argument is one of the names used in the Kendryte library. - */ -OUTPUT_ARCH( "riscv" ) - -/* - * The ENTRY command specifies the entry point (ie. first instruction to - * execute). The symbol _start is defined in crt0.S - */ -ENTRY(_start) - -/* - * The GROUP command is special since the listed archives will be - * searched repeatedly until there are no new undefined references. We - * need this since -lc depends on -lgloss and -lgloss depends on -lc. I - * thought gcc would automatically include -lgcc when needed, but - * in this file includes it explicitly here and I was seeing link errors - * without it. - */ -/* GROUP( -lc -lgloss -lgcc ) */ - -/* - * The linker only pays attention to the PHDRS command when generating - * an ELF output file. In other cases, the linker will simply ignore PHDRS. - */ -PHDRS -{ - ram_ro PT_LOAD; - ram_init PT_LOAD; - ram PT_NULL; -} - -/* - * This is where we specify how the input sections map to output - * sections. - */ -SECTIONS -{ - /* Program code segment, also known as a text segment */ - .text : - { - PROVIDE( _text = ABSOLUTE(.) ); - /* Initialization code segment */ - KEEP( *(.text.start) ) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - /* Normal code segment */ - *(.text .text.*) - *(.gnu.linkonce.t.*) - - . = ALIGN(8); - PROVIDE( _etext = ABSOLUTE(.) ); - } >ram AT>ram :ram_ro - - /* Read-only data segment */ - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >ram AT>ram :ram_ro - - . = ALIGN(8); - - /* Exception handling */ - .eh_frame : - { - KEEP (*(.eh_frame)) *(.eh_frame.*) - . = ALIGN(8); - } >ram AT>ram :ram_ro - .gnu_extab : { *(.gnu_extab) } >ram AT>ram :ram_ro - .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } >ram AT>ram :ram_ro - .exception_ranges : { *(.exception_ranges .exception_ranges*) } >ram AT>ram :ram_ro - - /* Init array and fini array */ - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >ram AT>ram :ram_ro - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - *(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors) - PROVIDE_HIDDEN (__init_array_end = .); - } >ram AT>ram :ram_ro - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >ram AT>ram :ram_ro - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >ram AT>ram :ram_ro - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >ram AT>ram :ram_ro - - . = ALIGN(8); - - .lalign : - { - . = ALIGN(8); - PROVIDE( _data_lma = . ); - } >ram AT>ram :ram_ro - - .dalign : - { - . = ALIGN(8); - PROVIDE( _data = . ); - } >ram AT>ram :ram_init - - . = ALIGN(8); - - /* .data, .sdata and .srodata segment */ - .data : - { - /* Writable data segment (.data segment) */ - *(.data .data.*) - *(.gnu.linkonce.d.*) - /* Have _gp point to middle of sdata/sbss to maximize displacement range */ - . = ALIGN(8); - PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800); - /* Writable small data segment (.sdata segment) */ - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - /* Read-only small data segment (.srodata segment) */ - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - /* Align _edata to cache line size */ - . = ALIGN(64); - PROVIDE( _edata = ABSOLUTE(.) ); - } >ram AT>ram :ram_init - - /* .bss and .sbss segment */ - .bss : - { - PROVIDE( _bss = ABSOLUTE(.) ); - /* Writable uninitialized small data segment (.sbss segment)*/ - *(.sbss .sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - /* Uninitialized writeable data section (.bss segment)*/ - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(8); - PROVIDE( _ebss = ABSOLUTE(.) ); - } >ram AT>ram :ram - - PROVIDE( _tls_data = ABSOLUTE(.) ); - /* - * Thread Local Storage (TLS) are per-thread global variables. - * Compilers such as GCC provide a __thread keyword to mark global - * variables as per-thread. Support is required in the program loader - * and thread creator. - */ - - /* Thread-local data segment, .tdata (initialized tls). */ - .tdata : - { - KEEP( *(.tdata.begin) ) - *(.tdata .tdata.*) - *(.gnu.linkonce.td.*) - KEEP( *(.tdata.end) ) - } >ram AT>ram :ram - - /* Thread-local bss segment, .tbss (zero-initialized tls). */ - .tbss : - { - *(.tbss .tbss.*) - *(.gnu.linkonce.tb.*) - KEEP( *(.tbss.end) ) - } >ram AT>ram :ram - - /* - * End of uninitalized data segement - * - * Actually the stack needs 16B alignment, and it won't hurt to also slightly - * increase the alignment to 32 or even 64 (cache line size). - * - * Align _heap_start to cache line size - */ - . = ALIGN(64); - PROVIDE( _end = ABSOLUTE(.) ); - /* Leave 2 holes for stack & TLS, the size can set in kconfig */ - - PROVIDE( _heap_start = ABSOLUTE(.) ); - /* - PROVIDE( _tp0 = (_end + 63) & (-64) ); - PROVIDE( _tp1 = _tp0 + _stack_size ); - PROVIDE( _sp0 = _tp0 + _stack_size ); - PROVIDE( _sp1 = _tp1 + _stack_size ); - */ - - /* Heap end is at the end of memory, the memory size can set in kconfig */ - PROVIDE( _heap_end = _ram_end ); -} - diff --git a/Kboot/lds/kendryte.ld b/Kboot/lds/kendryte.ld deleted file mode 100644 index fc99e70..0000000 --- a/Kboot/lds/kendryte.ld +++ /dev/null @@ -1,263 +0,0 @@ -/* - * The MEMORY command describes the location and size of blocks of memory - * in the target. You can use it to describe which memory regions may be - * used by the linker, and which memory regions it must avoid. - */ -MEMORY -{ - /* - * Memory with CPU cache. - * 64K CPU SRAM - */ - ram (wxari) : ORIGIN = 0x805E0000, LENGTH = 0x00008000 - /* - * Memory without CPU cache - * 64K CPU SRAM - */ - ram_nocache (wxari) : ORIGIN = 0x405E0000, LENGTH = 0x00008000 -} - -PROVIDE( _rom_start = ORIGIN(rom) ); -PROVIDE( _rom_end = ORIGIN(rom) + LENGTH(rom) ); -PROVIDE( _ram_start = ORIGIN(ram) ); -PROVIDE( _ram_end = ORIGIN(ram) + LENGTH(ram) ); -PROVIDE( _io_start = ORIGIN(ram_nocache) ); -PROVIDE( _io_end = _io_start + LENGTH(ram_nocache) ); - - -/* - * The OUTPUT_ARCH command specifies the machine architecture where the - * argument is one of the names used in the Kendryte library. - */ -OUTPUT_ARCH( "riscv" ) - -/* - * The ENTRY command specifies the entry point (ie. first instruction to - * execute). The symbol _start is defined in crt0.S - */ -ENTRY(_start) - -/* - * The GROUP command is special since the listed archives will be - * searched repeatedly until there are no new undefined references. We - * need this since -lc depends on -lgloss and -lgloss depends on -lc. I - * thought gcc would automatically include -lgcc when needed, but - * in this file includes it explicitly here and I was seeing link errors - * without it. - */ -/* GROUP( -lc -lgloss -lgcc ) */ - -/* - * The linker only pays attention to the PHDRS command when generating - * an ELF output file. In other cases, the linker will simply ignore PHDRS. - */ -PHDRS -{ - ram_ro PT_LOAD; - ram_init PT_LOAD; - ram PT_NULL; -} - -/* - * This is where we specify how the input sections map to output - * sections. - */ -SECTIONS -{ - /* Program code segment, also known as a text segment */ - .text : - { - PROVIDE( _text = ABSOLUTE(.) ); - /* Initialization code segment */ - KEEP( *(.text.start) ) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - /* Normal code segment */ - *(.text .text.*) - *(.gnu.linkonce.t.*) - - . = ALIGN(8); - PROVIDE( _etext = ABSOLUTE(.) ); - } >ram AT>ram :ram_ro - - /* Read-only data segment */ - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >ram AT>ram :ram_ro - - . = ALIGN(8); - - /* Exception handling */ - .eh_frame : - { - KEEP (*(.eh_frame)) *(.eh_frame.*) - . = ALIGN(8); - } >ram AT>ram :ram_ro - .gnu_extab : { *(.gnu_extab) } >ram AT>ram :ram_ro - .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } >ram AT>ram :ram_ro - .exception_ranges : { *(.exception_ranges .exception_ranges*) } >ram AT>ram :ram_ro - - /* Init array and fini array */ - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >ram AT>ram :ram_ro - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - *(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors) - PROVIDE_HIDDEN (__init_array_end = .); - } >ram AT>ram :ram_ro - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >ram AT>ram :ram_ro - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >ram AT>ram :ram_ro - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >ram AT>ram :ram_ro - - . = ALIGN(8); - - .lalign : - { - . = ALIGN(8); - PROVIDE( _data_lma = . ); - } >ram AT>ram :ram_ro - - .dalign : - { - . = ALIGN(8); - PROVIDE( _data = . ); - } >ram AT>ram :ram_init - - . = ALIGN(8); - - /* .data, .sdata and .srodata segment */ - .data : - { - /* Writable data segment (.data segment) */ - *(.data .data.*) - *(.gnu.linkonce.d.*) - /* Have _gp point to middle of sdata/sbss to maximize displacement range */ - . = ALIGN(8); - PROVIDE( __global_pointer$ = ABSOLUTE(.) + 0x800); - /* Writable small data segment (.sdata segment) */ - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - /* Read-only small data segment (.srodata segment) */ - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - /* Align _edata to cache line size */ - . = ALIGN(64); - PROVIDE( _edata = ABSOLUTE(.) ); - } >ram AT>ram :ram_init - - /* .bss and .sbss segment */ - .bss : - { - PROVIDE( _bss = ABSOLUTE(.) ); - /* Writable uninitialized small data segment (.sbss segment)*/ - *(.sbss .sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - /* Uninitialized writeable data section (.bss segment)*/ - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(8); - PROVIDE( _ebss = ABSOLUTE(.) ); - } >ram AT>ram :ram - - PROVIDE( _tls_data = ABSOLUTE(.) ); - /* - * Thread Local Storage (TLS) are per-thread global variables. - * Compilers such as GCC provide a __thread keyword to mark global - * variables as per-thread. Support is required in the program loader - * and thread creator. - */ - - /* Thread-local data segment, .tdata (initialized tls). */ - .tdata : - { - KEEP( *(.tdata.begin) ) - *(.tdata .tdata.*) - *(.gnu.linkonce.td.*) - KEEP( *(.tdata.end) ) - } >ram AT>ram :ram - - /* Thread-local bss segment, .tbss (zero-initialized tls). */ - .tbss : - { - *(.tbss .tbss.*) - *(.gnu.linkonce.tb.*) - KEEP( *(.tbss.end) ) - } >ram AT>ram :ram - - /* - * End of uninitalized data segement - * - * Actually the stack needs 16B alignment, and it won't hurt to also slightly - * increase the alignment to 32 or even 64 (cache line size). - * - * Align _heap_start to cache line size - */ - . = ALIGN(64); - PROVIDE( _end = ABSOLUTE(.) ); - /* Leave 2 holes for stack & TLS, the size can set in kconfig */ - - PROVIDE( _heap_start = ABSOLUTE(.) ); - /* - PROVIDE( _tp0 = (_end + 63) & (-64) ); - PROVIDE( _tp1 = _tp0 + _stack_size ); - PROVIDE( _sp0 = _tp0 + _stack_size ); - PROVIDE( _sp1 = _tp1 + _stack_size ); - */ - - /* Heap end is at the end of memory, the memory size can set in kconfig */ - PROVIDE( _heap_end = _ram_end ); -} - diff --git a/Kboot/lib/CMakeLists.txt b/Kboot/lib/CMakeLists.txt deleted file mode 100644 index c2a2e97..0000000 --- a/Kboot/lib/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -#project(maix_drivers) - -# create driver library - -FILE(GLOB_RECURSE LIB_SRC - "${CMAKE_CURRENT_LIST_DIR}/*.h" - "${CMAKE_CURRENT_LIST_DIR}/*.hpp" - "${CMAKE_CURRENT_LIST_DIR}/*.c" - "${CMAKE_CURRENT_LIST_DIR}/*.cpp" - "${CMAKE_CURRENT_LIST_DIR}/*.s" - "${CMAKE_CURRENT_LIST_DIR}/*.S" - ) - -FILE(GLOB_RECURSE ASSEMBLY_FILES - "${CMAKE_CURRENT_LIST_DIR}/*.s" - "${CMAKE_CURRENT_LIST_DIR}/*.S" - ) - -include_directories(${SDK_ROOT}/third_party/xtl/include) -include_directories(${CMAKE_CURRENT_LIST_DIR}/drivers/include ${CMAKE_CURRENT_LIST_DIR}/bsp/include ${CMAKE_CURRENT_LIST_DIR}/nncase/include) - -SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C) -SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64") - -ADD_LIBRARY(kendryte - ${LIB_SRC} - ) -SET_TARGET_PROPERTIES(kendryte PROPERTIES LINKER_LANGUAGE C) diff --git a/Kboot/src/bootloader_hi/README.md b/Kboot/src/bootloader_hi/README.md deleted file mode 100644 index b7e29fc..0000000 --- a/Kboot/src/bootloader_hi/README.md +++ /dev/null @@ -1,205 +0,0 @@ -# Kboot - -**Kboot** is a small applications (< 8KB) which enables loading and executing applications from any K210 SPI Flash location. - -## Features - -* load and execute K210 application stored on any location in SPI Flash -* application to be loaded is chosen from the list of available applications in **Kboot configuration sector** -* multiple criteria application validity check is performed when selecting the application -* if no valid application is found **default application** is loaded and executed -* The **interactive mode** can be enabled in which,based on the specific **Pin** state, the user can choose which application to load and execute -
- -## Boot process - -* After reset **Kboot** application is loaded by **K210 ROM** to sram address **`0x80000000`** and executed -* SPI Flash driver is initialized in **XiP** mode -* If allowed by configuration, **Boot Pin** state is checked and saved, if Boot Pin is activated **interactive mode** is enabled -* **Configuration sector** is scanned for valid applications, the following actions are performed: - * Configuration entry ID is checked - * Application Flash address is cheched for valid range - * Application size is checked for valid range - * Application flags are saved - * Application _Flash block_ ***** is checked for valid format - * If **CRC32** flag is set, application's crc32 is calculated and checked - * If **SHA256** flag is set, application's SHA256 hash is calculated and checked -* If all checks passes, the application is marked as **valid** -* If **not in interactive mode**, configuration sector scan is terminated as soon as the first valid, flagged as **active** application is found and that application is loaded and executed -* If in **interactive mode**, all configuration sector entries are scanned and the user is prompted to select which one to load and execute -* If **no valid application** is found, the **default application** is loaded and executed - -> ***** each application stored in SPI Flash has the following format: -> -> | Byte offset | Size | Name | Content | -> | ---: | ---: | :---: | :--- | -> | `0` | `1` | AES_FLAG | AES cipher flag, for use with **Kboot** must be `0` | -> | `1` | `4` | APP_SIZE | EApplication code size | -> | `5` | `APP_SIZE` | APP_CODE | Application code | -> | `APP_SIZE + 5` | `32` | SHA_HASH | Application SHA256 hash | -> -> All applications flashed with **Kflash** have such format. - -
- -## K210 SPI Flash layout - -The following SPI Flash layout must be used when using **Kboot* - -| From | To | Length | Comment | -| ---: | ---: | ---: | :--- | -| `0x00000000` | `0x0000FFFF` | 64K | **Kboot** application code | -| `0x00010000` | `0x0001FFFF` | 64K | reserved for future use | -| `0x00020000` | `0x00020FFF` | 4K | main **boot configuration** sector | -| `0x00021000` | `0x00021FFF` | 4K | backup **boot configuration** sector | -| `0x00022000` | `0x0002FFFF` | 56K | reserved, user data etc. | -| `0x00030000` | `0x0007FFFF` | 320K | **default application** code | -| `0x00080000` | `Flash end` | --- | user area, application(s) code, file system(s), user data etc. | - -
- -## **Boot configuration** sector - -Boot configuration used by **Kboot** is stored in one SPI Flash sector (4KB) at fixed Flash address.
-One **backup** configuration sector is also used for security reasons.
- -The configuration sector consists of **`8`** application entries occupying **`32`** bytes each + 32bit value, the configuration flags.
- -Configuration sector layout: - -| Offset | To | Length | Comment | -| ---: | ---: | ---: | :--- | -| `0x000` | `01F` | `32` | application entry #0 | -| `0x020` | `03F` | `32` | application entry #1 | -| `0x040` | `05F` | `32` | application entry #2 | -| `0x060` | `07F` | `32` | application entry #3 | -| `0x080` | `09F` | `32` | application entry #4 | -| `0x0A0` | `0BF` | `32` | application entry #5 | -| `0x0C0` | `0DF` | `32` | application entry #6 | -| `0x0E0` | `0FF` | `32` | application entry #7 | -| `0x100` | `103` | `4` | **config flags** | -| `0x104` | `11F` | `4` | reserved | -| `0x120` | `11F` | `4` | not used, user data | -
- -The format of each application entry in configuration sector is as follows: - -| Offset | Length | Comment | -| ---: | ---: | :--- | -| `0` | `4` | Configuration entry **ID** (bits 4-31) + entry **flags** (bits 0-4) | -| `4` | `4` | Application address in SPI Flash | -| `8` | `4` | Application size in SPI Flash. This is the size of the application's **`.bin`** file | -| `12` | `4` | Application's CRC32 value (32bits) | -| `16` | `16` | Null terminated application name/description | - -_Notes:_
-Configuration entry **ID** must have a value of **`0x5AA5D0C0`** for entry to recognized as valid.
-Application addres must be in range **`0x80000`** ~ **`0x800000`** ( 512KB ~ 8MB ).
-Application size must be in range **`0x4000`** ~ **`0x300000`** ( 16KB ~ 3MB ).
-Application CRC32 value is used only if **CRC32** flag is set.

- -If **config flags** at offset `0x100` in **configuration sector** is set to configuration entry **ID** (**`0x5AA5D0C0`**), **interractive mode** will be disabled, **boot Pin* and nothing will be printed during the boot process. -Configuration entry **flags**: - -| Bit | Comment | -| :---: | :--- | -| `0` | **Active** flag, if set the application will be loaded and executed.
If multiple entries have **active** flag set, the first one will be loaded ad executed | -| `1` | **CRC32** flag, if set the application's CRC32 value will be calculated and compared with the value in the configuration entry | -| `2` | **AES256** flag, if set the application's AES256 hash value will be calculated and compared with the value stored in flash after the application code (`SHA_HASH`) | -| `3` | Not used, reserved | - -**_Warning:_** all 32-bit values in the configuration sector entries must be written in **big-endian** format. - -
- -## Default application - -If in the boot process **no valid application** was found in the **configuration sector**, the **default application** is loaded and executed.
-If the **default application** is loaded that usually means some error occured and the system may be considered unusable.
-**_The default application should try to check what was wrong and try to correct the issue._** - -
- -## Building the applications to be used with _Kboot_ - -Importand thing to remember is that the applications loaded and executed by **Kboot** are **NOT loaded** at the default K210 SRAM address **(`0x80000000`)**, but at address **`0x80002000`** !
-Therefore, when building the application, it must be **linked** for start address **`0x80002000`**.
- -Fortunatelly, it is quite simple to do it, only a slight modification of the linker script is needed.
-The linker script is usually called **kendryte.ld** and it is located in the **Kendryte SDK** **_lds_** directory.
-The beginning of that file looks like this: -``` -/* - * The MEMORY command describes the location and size of blocks of memory - * in the target. You can use it to describe which memory regions may be - * used by the linker, and which memory regions it must avoid. - */ -MEMORY -{ - /* - * Memory with CPU cache. - *6M CPU SRAM - */ - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024) - /* - * Memory without CPU cache - * 6M CPU SRAM - */ - ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024) -} -``` - -The only entries which has to be changed are **`ORIGIN`** and **`LENGTH`**.
-Change:
-`ORIGIN = 0x80000000` to **`ORIGIN = 0x80002000`**
-`ORIGIN = 0x40000000` to **`ORIGIN = 0x40002000`**
-`LENGTH = (6 * 1024 * 1024)` to **`LENGTH = (6 * 1024 * 1024 - 0x2000)`**
- -and build the application as usual.
- -The beginning of the modified **kendryte.ld** should look like this: -```console -/* - * The MEMORY command describes the location and size of blocks of memory - * in the target. You can use it to describe which memory regions may be - * used by the linker, and which memory regions it must avoid. - */ -MEMORY -{ - /* - * Memory with CPU cache. - *6M CPU SRAM - */ - ram (wxa!ri) : ORIGIN = 0x80002000, LENGTH = (6 * 1024 * 1024 - 0x2000) - /* - * Memory without CPU cache - * 6M CPU SRAM - */ - ram_nocache (wxa!ri) : ORIGIN = 0x40002000, LENGTH = (6 * 1024 * 1024 - 0x2000) -} -``` - -**_When building the application also check if any part of the code depends on application start address in SRAM._**
-For most applications it is not the case. - -

- -## Usage - -Flashing the application(s) to SPI Flash and manipulating the boot **configuration sector** should be performed from the user application.
-Accessing SPI flash from K210 application is quite easy and reliable. - - - -### Example - -**Application firmware update** - -* The condition to update the firmware is detected by the application -* Load the **boot configuration** sector, check its integrity and check the flash address and size of the currently running application -* Flash the new firmware to the **not used** SPI Flash area. The new firmware can be downloaded from remote server using WiFi or GSM, loaded from SD Card, etc ...
Use the **application block** format described above.
The application can be flashed **without** SHA256 hash, in that case do not set the **`SHA256`** flag. -* Calculate new firmware's CRC32 and/or SHA256 hash if needed. -* Flash the current **main** boot configuration sector to the **backup** boot configuration sector and check it.
It will be used by **Kboot** in case the **main** boot configuration sector which we are going to write is corrupted. -* Update (add or change entry) in the boot configuration sector with the new firmware information, set the new firmware as active and the old firmware as inactive and flash the configuration sector. -* Reset (reboot) the system to start the new firmware. - diff --git a/Kboot/src/bootloader_hi/crt.S b/Kboot/src/bootloader_hi/crt.S deleted file mode 100644 index e06e7d7..0000000 --- a/Kboot/src/bootloader_hi/crt.S +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2019 LoBo (https://github.com/loboris) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - - -.section .text.start, "ax", @progbits -.globl _start -_start: -# Jump directly to 'main' - - j main -.ascii "Kboot_v1.4.1" -.word 0 diff --git a/Kboot/src/bootloader_hi/fpioa.c b/Kboot/src/bootloader_hi/fpioa.c deleted file mode 100644 index 1cc8f5d..0000000 --- a/Kboot/src/bootloader_hi/fpioa.c +++ /dev/null @@ -1,4932 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include -#include -#include "fpioa.h" -#include "sysctl.h" - -volatile fpioa_t *const fpioa = (volatile fpioa_t *)FPIOA_BASE_ADDR; - -/** - * @brief Internal used FPIOA function initialize cell - * - * This is NOT fpioa_io_config_t, can't assign directly - * - */ -typedef struct _fpioa_assign_t -{ - uint32_t ch_sel : 8; - /* Channel select from 256 input. */ - uint32_t ds : 4; - /* Driving selector. */ - uint32_t oe_en : 1; - /* Static output enable, will AND with OE_INV. */ - uint32_t oe_inv : 1; - /* Invert output enable. */ - uint32_t do_sel : 1; - /* Data output select: 0 for DO, 1 for OE. */ - uint32_t do_inv : 1; - /* Invert the result of data output select (DO_SEL). */ - uint32_t pu : 1; - /* Pull up enable. 0 for nothing, 1 for pull up. */ - uint32_t pd : 1; - /* Pull down enable. 0 for nothing, 1 for pull down. */ - uint32_t resv0 : 1; - /* Reserved bits. */ - uint32_t sl : 1; - /* Slew rate control enable. */ - uint32_t ie_en : 1; - /* Static input enable, will AND with IE_INV. */ - uint32_t ie_inv : 1; - /* Invert input enable. */ - uint32_t di_inv : 1; - /* Invert Data input. */ - uint32_t st : 1; - /* Schmitt trigger. */ - uint32_t tie_en : 1; - /* Input tie enable, 1 for enable, 0 for disable. */ - uint32_t tie_val : 1; - /* Input tie value, 1 for high, 0 for low. */ - uint32_t resv1 : 5; - /* Reserved bits. */ - uint32_t pad_di : 1; - /* Read current PAD's data input. */ -} __attribute__((packed, aligned(4))) fpioa_assign_t; - -/* Function list */ -static const fpioa_assign_t function_config[FUNC_MAX] = - { - {.ch_sel = FUNC_JTAG_TCLK, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_JTAG_TDI, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_JTAG_TMS, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_JTAG_TDO, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D5, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D6, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_D7, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_SS0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_SS1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_SS2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_SS3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_ARB, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 1, - .tie_val = 1, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI0_SCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UARTHS_RX, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UARTHS_TX, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV6, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV7, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CLK_SPI1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CLK_I2C1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS5, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS6, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS7, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS8, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS9, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS10, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS11, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS12, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS13, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS14, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS15, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS16, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS17, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS18, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS19, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS20, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS21, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS22, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS23, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS24, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS25, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS26, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS27, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS28, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS29, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS30, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIOHS31, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO5, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO6, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_GPIO7, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_RX, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_TX, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_RX, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_TX, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_RX, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_TX, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D5, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D6, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_D7, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_SS0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_SS1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_SS2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_SS3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_ARB, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 1, - .tie_val = 1, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI1_SCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI_SLAVE_D0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 1, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI_SLAVE_SS, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SPI_SLAVE_SCLK, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_MCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_SCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_WS, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_IN_D0, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_IN_D1, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_IN_D2, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_IN_D3, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_OUT_D0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_OUT_D1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_OUT_D2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S0_OUT_D3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_MCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_SCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_WS, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_IN_D0, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_IN_D1, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_IN_D2, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_IN_D3, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_OUT_D0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_OUT_D1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_OUT_D2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S1_OUT_D3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_MCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_SCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_WS, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_IN_D0, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_IN_D1, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_IN_D2, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_IN_D3, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_OUT_D0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_OUT_D1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_OUT_D2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2S2_OUT_D3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV0, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV1, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV2, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV3, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV4, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_RESV5, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2C0_SCLK, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2C0_SDA, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2C1_SCLK, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2C1_SDA, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2C2_SCLK, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_I2C2_SDA, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_XCLK, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_RST, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_PWDN, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_VSYNC, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_HREF, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_PCLK, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D0, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D1, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D2, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D3, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D4, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D5, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D6, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CMOS_D7, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SCCB_SCLK, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_SCCB_SDA, - .ds = 0x0, - .oe_en = 1, - .oe_inv = 1, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_CTS, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_DSR, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_DCD, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_RI, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_SIR_IN, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_DTR, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_RTS, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_OUT2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_OUT1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_SIR_OUT, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_BAUD, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_RE, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_DE, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART1_RS485_EN, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_CTS, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_DSR, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_DCD, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_RI, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_SIR_IN, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_DTR, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_RTS, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_OUT2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_OUT1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_SIR_OUT, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_BAUD, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_RE, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_DE, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART2_RS485_EN, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_CTS, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_DSR, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_DCD, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_RI, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_SIR_IN, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_DTR, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_RTS, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_OUT2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_OUT1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_SIR_OUT, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_BAUD, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_RE, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_DE, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_UART3_RS485_EN, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER0_TOGGLE1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER0_TOGGLE2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER0_TOGGLE3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER0_TOGGLE4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER1_TOGGLE1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER1_TOGGLE2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER1_TOGGLE3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER1_TOGGLE4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER2_TOGGLE1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER2_TOGGLE2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER2_TOGGLE3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_TIMER2_TOGGLE4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CLK_SPI2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CLK_I2C2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL5, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL6, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL7, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL8, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL9, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL10, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL11, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL12, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL13, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL14, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 1, - .pd = 0, - .resv1 = 0, - .sl = 1, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL15, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL16, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL17, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_CONSTANT, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_INTERNAL18, - .ds = 0x0, - .oe_en = 0, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 1, - .ie_inv = 0, - .di_inv = 0, - .st = 1, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG0, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG1, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG2, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG3, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG4, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG5, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG6, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG7, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG8, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG9, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG10, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG11, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG12, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG13, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG14, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG15, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG16, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG17, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG18, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG19, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG20, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG21, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG22, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG23, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG24, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG25, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG26, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG27, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG28, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG29, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG30, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, - {.ch_sel = FUNC_DEBUG31, - .ds = 0xf, - .oe_en = 1, - .oe_inv = 0, - .do_sel = 0, - .do_inv = 0, - .pu = 0, - .pd = 0, - .resv1 = 0, - .sl = 0, - .ie_en = 0, - .ie_inv = 0, - .di_inv = 0, - .st = 0, - .tie_en = 0, - .tie_val = 0, - .resv0 = 0, - .pad_di = 0}, -}; - -int fpioa_init(void) -{ - int i = 0; - - /* Enable fpioa clock in system controller */ - //sysctl_clock_enable(SYSCTL_CLOCK_FPIOA); - - /* Initialize tie */ - fpioa_tie_t tie = {0}; - - /* Set tie enable and tie value */ - for(i = 0; i < FUNC_MAX; i++) - { - tie.en[i / 32] |= (function_config[i].tie_en << (i % 32)); - tie.val[i / 32] |= (function_config[i].tie_val << (i % 32)); - } - - /* Atomic write every 32bit register to fpioa function */ - for(i = 0; i < FUNC_MAX / 32; i++) - { - /* Set value before enable */ - fpioa->tie.val[i] = tie.val[i]; - fpioa->tie.en[i] = tie.en[i]; - } - - return 0; -} - -int fpioa_get_io(int number, fpioa_io_config_t *cfg) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO || cfg == NULL) - return -1; - /* Atomic read register */ - *cfg = fpioa->io[number]; - return 0; -} - -int fpioa_set_io(int number, fpioa_io_config_t *cfg) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO || cfg == NULL) - return -1; - /* Atomic write register */ - fpioa->io[number] = *cfg; - return 0; -} - -int fpioa_set_io_pull(int number, fpioa_pull_t pull) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO || pull >= FPIOA_PULL_MAX) - return -1; - - /* Atomic read register */ - fpioa_io_config_t cfg = fpioa->io[number]; - - switch(pull) - { - case FPIOA_PULL_NONE: - cfg.pu = 0; - cfg.pd = 0; - break; - case FPIOA_PULL_DOWN: - cfg.pu = 0; - cfg.pd = 1; - break; - case FPIOA_PULL_UP: - cfg.pu = 1; - cfg.pd = 0; - break; - default: - break; - } - /* Atomic write register */ - fpioa->io[number] = cfg; - return 0; -} - -int fpioa_get_io_pull(int number) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO) - return -1; - - fpioa_pull_t pull; - /* Atomic read register */ - fpioa_io_config_t cfg = fpioa->io[number]; - - if(cfg.pu == 0 && cfg.pd == 1) - pull = FPIOA_PULL_DOWN; - else if(cfg.pu == 1 && cfg.pd == 0) - pull = FPIOA_PULL_UP; - else - pull = FPIOA_PULL_NONE; - return pull; -} - -int fpioa_set_io_driving(int number, fpioa_driving_t driving) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO || driving >= FPIOA_DRIVING_MAX) - return -1; - - /* Atomic read register */ - fpioa_io_config_t cfg = fpioa->io[number]; - /* Set IO driving */ - cfg.ds = driving; - /* Atomic write register */ - fpioa->io[number] = cfg; - return 0; -} - -int fpioa_set_sl(int number, uint8_t sl_enable) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO) - return -1; - - /* Atomic read register */ - fpioa_io_config_t cfg = fpioa->io[number]; - /* Set IO slew rate */ - cfg.sl = sl_enable; - /* Atomic write register */ - fpioa->io[number] = cfg; - return 0; -} - -int fpioa_set_st(int number, uint8_t st_enable) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO) - return -1; - - /* Atomic read register */ - fpioa_io_config_t cfg = fpioa->io[number]; - /* Set IO schmitt trigger */ - cfg.st = st_enable; - /* Atomic write register */ - fpioa->io[number] = cfg; - return 0; -} - -int fpioa_set_oe_inv(int number, uint8_t inv_enable) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO) - return -1; - - /* Atomic read register */ - fpioa_io_config_t cfg = fpioa->io[number]; - /* Set IO schmitt trigger */ - cfg.oe_inv = inv_enable; - /* Atomic write register */ - fpioa->io[number] = cfg; - return 0; -} - -int fpioa_get_io_driving(int number) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO) - return -1; - - return fpioa->io[number].ds; -} - -int fpioa_set_function_raw(int number, fpioa_function_t function) -{ - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO || function < 0 || function >= FUNC_MAX) - return -1; - /* Atomic write register */ - fpioa->io[number] = (const fpioa_io_config_t){ - .ch_sel = function_config[function].ch_sel, - .ds = function_config[function].ds, - .oe_en = function_config[function].oe_en, - .oe_inv = function_config[function].oe_inv, - .do_sel = function_config[function].do_sel, - .do_inv = function_config[function].do_inv, - .pu = function_config[function].pu, - .pd = function_config[function].pd, - .sl = function_config[function].sl, - .ie_en = function_config[function].ie_en, - .ie_inv = function_config[function].ie_inv, - .di_inv = function_config[function].di_inv, - .st = function_config[function].st, - /* resv and pad_di do not need initialization */ - }; - return 0; -} - -int fpioa_set_function(int number, fpioa_function_t function) -{ - uint8_t index = 0; - /* Check parameters */ - if(number < 0 || number >= FPIOA_NUM_IO || function < 0 || function >= FUNC_MAX) - return -1; - if(function == FUNC_RESV0) - { - fpioa_set_function_raw(number, FUNC_RESV0); - return 0; - } - /* Compare all IO */ - for(index = 0; index < FPIOA_NUM_IO; index++) - { - if((fpioa->io[index].ch_sel == function) && (index != number)) - fpioa_set_function_raw(index, FUNC_RESV0); - } - fpioa_set_function_raw(number, function); - return 0; -} - -int fpioa_set_tie_enable(fpioa_function_t function, int enable) -{ - /* Check parameters */ - if(function < 0 || function >= FUNC_MAX) - return -1; - /* Set tie enable */ - if(enable) - fpioa->tie.en[function / 32] |= (1UL << (function % 32)); - else - fpioa->tie.en[function / 32] &= (~(1UL << (function % 32))); - return 0; -} - -int fpioa_set_tie_value(fpioa_function_t function, int value) -{ - /* Check parameters */ - if(function < 0 || function >= FUNC_MAX) - return -1; - /* Set tie value */ - if(value) - fpioa->tie.val[function / 32] |= (1UL << (function % 32)); - else - fpioa->tie.val[function / 32] &= (~(1UL << (function % 32))); - return 0; -} - -int fpioa_get_io_by_function(fpioa_function_t function) -{ - int index = 0; - for(index = 0; index < FPIOA_NUM_IO; index++) - { - if(fpioa->io[index].ch_sel == function) - return index; - } - - return -1; -} diff --git a/Kboot/src/bootloader_hi/gpiohs.c b/Kboot/src/bootloader_hi/gpiohs.c deleted file mode 100644 index 273e23b..0000000 --- a/Kboot/src/bootloader_hi/gpiohs.c +++ /dev/null @@ -1,110 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "fpioa.h" -#include "gpiohs.h" -#include "sysctl.h" - -#define GPIOHS_MAX_PINNO 32 - -volatile gpiohs_t *const gpiohs = (volatile gpiohs_t *)GPIOHS_BASE_ADDR; - -/* -typedef struct _gpiohs_pin_instance -{ - size_t pin; - gpio_pin_edge_t edge; - void (*callback)(); - //plic_irq_callback_t gpiohs_callback; - void *context; -} gpiohs_pin_instance_t; - -static gpiohs_pin_instance_t pin_instance[32]; -*/ - -void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value) -{ - uint32_t org = (*bits) & ~mask; - *bits = org | (value & mask); -} - -void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value) -{ - set_bit(bits, mask << offset, value << offset); -} - -void set_gpio_bit(volatile uint32_t *bits, size_t offset, uint32_t value) -{ - set_bit_offset(bits, 1, offset, value); -} - -uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset) -{ - return ((*bits) & (mask << offset)) >> offset; -} - -uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset) -{ - return get_bit(bits, 1, offset); -} - - - - -void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode) -{ - int io_number = fpioa_get_io_by_function(FUNC_GPIOHS0 + pin); - - fpioa_pull_t pull = FPIOA_PULL_NONE; - uint32_t dir = 0; - - switch(mode) - { - case GPIO_DM_INPUT: - pull = FPIOA_PULL_NONE; - dir = 0; - break; - case GPIO_DM_INPUT_PULL_DOWN: - pull = FPIOA_PULL_DOWN; - dir = 0; - break; - case GPIO_DM_INPUT_PULL_UP: - pull = FPIOA_PULL_UP; - dir = 0; - break; - case GPIO_DM_OUTPUT: - pull = FPIOA_PULL_DOWN; - dir = 1; - break; - default: - break; - } - - fpioa_set_io_pull(io_number, pull); - volatile uint32_t *reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32; - volatile uint32_t *reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32; - set_gpio_bit(reg_d, pin, 0); - set_gpio_bit(reg, pin, 1); -} - -gpio_pin_value_t gpiohs_get_pin(uint8_t pin) -{ - return get_gpio_bit(gpiohs->input_val.u32, pin); -} - -void gpiohs_set_pin(uint8_t pin, gpio_pin_value_t value) -{ - set_gpio_bit(gpiohs->output_val.u32, pin, value); -} - diff --git a/Kboot/src/bootloader_hi/include/config.h b/Kboot/src/bootloader_hi/include/config.h deleted file mode 100644 index 70f2301..0000000 --- a/Kboot/src/bootloader_hi/include/config.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Defined from MicroPython build - */ -#define FIRMWARE_SIZE (0x300000UL) -#define BOOT_PIN -1 - diff --git a/Kboot/src/bootloader_hi/include/encoding.h b/Kboot/src/bootloader_hi/include/encoding.h deleted file mode 100644 index 3eebee5..0000000 --- a/Kboot/src/bootloader_hi/include/encoding.h +++ /dev/null @@ -1,1325 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001U -#define MSTATUS_SIE 0x00000002U -#define MSTATUS_HIE 0x00000004U -#define MSTATUS_MIE 0x00000008U -#define MSTATUS_UPIE 0x00000010U -#define MSTATUS_SPIE 0x00000020U -#define MSTATUS_HPIE 0x00000040U -#define MSTATUS_MPIE 0x00000080U -#define MSTATUS_SPP 0x00000100U -#define MSTATUS_HPP 0x00000600U -#define MSTATUS_MPP 0x00001800U -#define MSTATUS_FS 0x00006000U -#define MSTATUS_XS 0x00018000U -#define MSTATUS_MPRV 0x00020000U -#define MSTATUS_PUM 0x00040000U -#define MSTATUS_MXR 0x00080000U -#define MSTATUS_VM 0x1F000000U -#define MSTATUS32_SD 0x80000000U -#define MSTATUS64_SD 0x8000000000000000U - -#define SSTATUS_UIE 0x00000001U -#define SSTATUS_SIE 0x00000002U -#define SSTATUS_UPIE 0x00000010U -#define SSTATUS_SPIE 0x00000020U -#define SSTATUS_SPP 0x00000100U -#define SSTATUS_FS 0x00006000U -#define SSTATUS_XS 0x00018000U -#define SSTATUS_PUM 0x00040000U -#define SSTATUS32_SD 0x80000000U -#define SSTATUS64_SD 0x8000000000000000U - -#define DCSR_XDEBUGVER (3U << 30) -#define DCSR_NDRESET (1U << 29) -#define DCSR_FULLRESET (1U << 28) -#define DCSR_EBREAKM (1U << 15) -#define DCSR_EBREAKH (1U << 14) -#define DCSR_EBREAKS (1U << 13) -#define DCSR_EBREAKU (1U << 12) -#define DCSR_STOPCYCLE (1U << 10) -#define DCSR_STOPTIME (1U << 9) -#define DCSR_CAUSE (7U << 6) -#define DCSR_DEBUGINT (1U << 5) -#define DCSR_HALT (1U << 3) -#define DCSR_STEP (1U << 2) -#define DCSR_PRV (3U << 0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_SELECT (1U << 19) -#define MCONTROL_TIMING (1U << 18) -#define MCONTROL_ACTION (0x3fU << 12) -#define MCONTROL_CHAIN (1U << 11) -#define MCONTROL_MATCH (0xfU << 7) -#define MCONTROL_M (1U << 6) -#define MCONTROL_H (1U << 5) -#define MCONTROL_S (1U << 4) -#define MCONTROL_U (1U << 3) -#define MCONTROL_EXECUTE (1U << 2) -#define MCONTROL_STORE (1U << 1) -#define MCONTROL_LOAD (1U << 0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1U << IRQ_S_SOFT) -#define MIP_HSIP (1U << IRQ_H_SOFT) -#define MIP_MSIP (1U << IRQ_M_SOFT) -#define MIP_STIP (1U << IRQ_S_TIMER) -#define MIP_HTIP (1U << IRQ_H_TIMER) -#define MIP_MTIP (1U << IRQ_M_TIMER) -#define MIP_SEIP (1U << IRQ_S_EXT) -#define MIP_HEIP (1U << IRQ_H_EXT) -#define MIP_MEIP (1U << IRQ_M_EXT) - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000U -#define DEFAULT_NMIVEC 0x00001004U -#define DEFAULT_MTVEC 0x00001010U -#define CONFIG_STRING_ADDR 0x0000100CU -#define EXT_IO_BASE 0x40000000U -#define DRAM_BASE 0x80000000U - -/* page table entry (PTE) fields */ -#define PTE_V 0x001U /* Valid */ -#define PTE_R 0x002U /* Read */ -#define PTE_W 0x004U /* Write */ -#define PTE_X 0x008U /* Execute */ -#define PTE_U 0x010U /* User */ -#define PTE_G 0x020U /* Global */ -#define PTE_A 0x040U /* Accessed */ -#define PTE_D 0x080U /* Dirty */ -#define PTE_SOFT 0x300U /* Reserved for Software */ - -#define PTE_PPN_SHIFT 10 - -#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#if defined(__riscv) - -#if defined(__riscv64) -#define MSTATUS_SD MSTATUS64_SD -#define SSTATUS_SD SSTATUS64_SD -#define RISCV_PGLEVEL_BITS 9 -#else -#define MSTATUS_SD MSTATUS32_SD -#define SSTATUS_SD SSTATUS32_SD -#define RISCV_PGLEVEL_BITS 10 -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#if defined(__GNUC__) - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define read_time() read_csr(mtime) -#define read_cycle() read_csr(mcycle) -#define current_coreid() read_csr(mhartid) - -#endif - -#endif - -#endif - -#endif - -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63U -#define MASK_BEQ 0x707fU -#define MATCH_BNE 0x1063U -#define MASK_BNE 0x707fU -#define MATCH_BLT 0x4063U -#define MASK_BLT 0x707fU -#define MATCH_BGE 0x5063U -#define MASK_BGE 0x707fU -#define MATCH_BLTU 0x6063U -#define MASK_BLTU 0x707fU -#define MATCH_BGEU 0x7063U -#define MASK_BGEU 0x707fU -#define MATCH_JALR 0x67U -#define MASK_JALR 0x707fU -#define MATCH_JAL 0x6fU -#define MASK_JAL 0x7fU -#define MATCH_LUI 0x37U -#define MASK_LUI 0x7fU -#define MATCH_AUIPC 0x17U -#define MASK_AUIPC 0x7fU -#define MATCH_ADDI 0x13U -#define MASK_ADDI 0x707fU -#define MATCH_SLLI 0x1013U -#define MASK_SLLI 0xfc00707fU -#define MATCH_SLTI 0x2013U -#define MASK_SLTI 0x707fU -#define MATCH_SLTIU 0x3013U -#define MASK_SLTIU 0x707fU -#define MATCH_XORI 0x4013U -#define MASK_XORI 0x707fU -#define MATCH_SRLI 0x5013U -#define MASK_SRLI 0xfc00707fU -#define MATCH_SRAI 0x40005013U -#define MASK_SRAI 0xfc00707fU -#define MATCH_ORI 0x6013U -#define MASK_ORI 0x707fU -#define MATCH_ANDI 0x7013U -#define MASK_ANDI 0x707fU -#define MATCH_ADD 0x33U -#define MASK_ADD 0xfe00707fU -#define MATCH_SUB 0x40000033U -#define MASK_SUB 0xfe00707fU -#define MATCH_SLL 0x1033U -#define MASK_SLL 0xfe00707fU -#define MATCH_SLT 0x2033U -#define MASK_SLT 0xfe00707fU -#define MATCH_SLTU 0x3033U -#define MASK_SLTU 0xfe00707fU -#define MATCH_XOR 0x4033U -#define MASK_XOR 0xfe00707fU -#define MATCH_SRL 0x5033U -#define MASK_SRL 0xfe00707fU -#define MATCH_SRA 0x40005033U -#define MASK_SRA 0xfe00707fU -#define MATCH_OR 0x6033U -#define MASK_OR 0xfe00707fU -#define MATCH_AND 0x7033U -#define MASK_AND 0xfe00707fU -#define MATCH_ADDIW 0x1bU -#define MASK_ADDIW 0x707fU -#define MATCH_SLLIW 0x101bU -#define MASK_SLLIW 0xfe00707fU -#define MATCH_SRLIW 0x501bU -#define MASK_SRLIW 0xfe00707fU -#define MATCH_SRAIW 0x4000501bU -#define MASK_SRAIW 0xfe00707fU -#define MATCH_ADDW 0x3bU -#define MASK_ADDW 0xfe00707fU -#define MATCH_SUBW 0x4000003bU -#define MASK_SUBW 0xfe00707fU -#define MATCH_SLLW 0x103bU -#define MASK_SLLW 0xfe00707fU -#define MATCH_SRLW 0x503bU -#define MASK_SRLW 0xfe00707fU -#define MATCH_SRAW 0x4000503bU -#define MASK_SRAW 0xfe00707fU -#define MATCH_LB 0x3U -#define MASK_LB 0x707fU -#define MATCH_LH 0x1003U -#define MASK_LH 0x707fU -#define MATCH_LW 0x2003U -#define MASK_LW 0x707fU -#define MATCH_LD 0x3003U -#define MASK_LD 0x707fU -#define MATCH_LBU 0x4003U -#define MASK_LBU 0x707fU -#define MATCH_LHU 0x5003U -#define MASK_LHU 0x707fU -#define MATCH_LWU 0x6003U -#define MASK_LWU 0x707fU -#define MATCH_SB 0x23U -#define MASK_SB 0x707fU -#define MATCH_SH 0x1023U -#define MASK_SH 0x707fU -#define MATCH_SW 0x2023U -#define MASK_SW 0x707fU -#define MATCH_SD 0x3023U -#define MASK_SD 0x707fU -#define MATCH_FENCE 0xfU -#define MASK_FENCE 0x707fU -#define MATCH_FENCE_I 0x100fU -#define MASK_FENCE_I 0x707fU -#define MATCH_MUL 0x2000033U -#define MASK_MUL 0xfe00707fU -#define MATCH_MULH 0x2001033U -#define MASK_MULH 0xfe00707fU -#define MATCH_MULHSU 0x2002033U -#define MASK_MULHSU 0xfe00707fU -#define MATCH_MULHU 0x2003033U -#define MASK_MULHU 0xfe00707fU -#define MATCH_DIV 0x2004033U -#define MASK_DIV 0xfe00707fU -#define MATCH_DIVU 0x2005033U -#define MASK_DIVU 0xfe00707fU -#define MATCH_REM 0x2006033U -#define MASK_REM 0xfe00707fU -#define MATCH_REMU 0x2007033U -#define MASK_REMU 0xfe00707fU -#define MATCH_MULW 0x200003bU -#define MASK_MULW 0xfe00707fU -#define MATCH_DIVW 0x200403bU -#define MASK_DIVW 0xfe00707fU -#define MATCH_DIVUW 0x200503bU -#define MASK_DIVUW 0xfe00707fU -#define MATCH_REMW 0x200603bU -#define MASK_REMW 0xfe00707fU -#define MATCH_REMUW 0x200703bU -#define MASK_REMUW 0xfe00707fU -#define MATCH_AMOADD_W 0x202fU -#define MASK_AMOADD_W 0xf800707fU -#define MATCH_AMOXOR_W 0x2000202fU -#define MASK_AMOXOR_W 0xf800707fU -#define MATCH_AMOOR_W 0x4000202fU -#define MASK_AMOOR_W 0xf800707fU -#define MATCH_AMOAND_W 0x6000202fU -#define MASK_AMOAND_W 0xf800707fU -#define MATCH_AMOMIN_W 0x8000202fU -#define MASK_AMOMIN_W 0xf800707fU -#define MATCH_AMOMAX_W 0xa000202fU -#define MASK_AMOMAX_W 0xf800707fU -#define MATCH_AMOMINU_W 0xc000202fU -#define MASK_AMOMINU_W 0xf800707fU -#define MATCH_AMOMAXU_W 0xe000202fU -#define MASK_AMOMAXU_W 0xf800707fU -#define MATCH_AMOSWAP_W 0x800202fU -#define MASK_AMOSWAP_W 0xf800707fU -#define MATCH_LR_W 0x1000202fU -#define MASK_LR_W 0xf9f0707fU -#define MATCH_SC_W 0x1800202fU -#define MASK_SC_W 0xf800707fU -#define MATCH_AMOADD_D 0x302fU -#define MASK_AMOADD_D 0xf800707fU -#define MATCH_AMOXOR_D 0x2000302fU -#define MASK_AMOXOR_D 0xf800707fU -#define MATCH_AMOOR_D 0x4000302fU -#define MASK_AMOOR_D 0xf800707fU -#define MATCH_AMOAND_D 0x6000302fU -#define MASK_AMOAND_D 0xf800707fU -#define MATCH_AMOMIN_D 0x8000302fU -#define MASK_AMOMIN_D 0xf800707fU -#define MATCH_AMOMAX_D 0xa000302fU -#define MASK_AMOMAX_D 0xf800707fU -#define MATCH_AMOMINU_D 0xc000302fU -#define MASK_AMOMINU_D 0xf800707fU -#define MATCH_AMOMAXU_D 0xe000302fU -#define MASK_AMOMAXU_D 0xf800707fU -#define MATCH_AMOSWAP_D 0x800302fU -#define MASK_AMOSWAP_D 0xf800707fU -#define MATCH_LR_D 0x1000302fU -#define MASK_LR_D 0xf9f0707fU -#define MATCH_SC_D 0x1800302fU -#define MASK_SC_D 0xf800707fU -#define MATCH_ECALL 0x73U -#define MASK_ECALL 0xffffffffU -#define MATCH_EBREAK 0x100073U -#define MASK_EBREAK 0xffffffffU -#define MATCH_URET 0x200073U -#define MASK_URET 0xffffffffU -#define MATCH_SRET 0x10200073U -#define MASK_SRET 0xffffffffU -#define MATCH_HRET 0x20200073U -#define MASK_HRET 0xffffffffU -#define MATCH_MRET 0x30200073U -#define MASK_MRET 0xffffffffU -#define MATCH_DRET 0x7b200073U -#define MASK_DRET 0xffffffffU -#define MATCH_SFENCE_VM 0x10400073U -#define MASK_SFENCE_VM 0xfff07fffU -#define MATCH_WFI 0x10500073U -#define MASK_WFI 0xffffffffU -#define MATCH_CSRRW 0x1073U -#define MASK_CSRRW 0x707fU -#define MATCH_CSRRS 0x2073U -#define MASK_CSRRS 0x707fU -#define MATCH_CSRRC 0x3073U -#define MASK_CSRRC 0x707fU -#define MATCH_CSRRWI 0x5073U -#define MASK_CSRRWI 0x707fU -#define MATCH_CSRRSI 0x6073U -#define MASK_CSRRSI 0x707fU -#define MATCH_CSRRCI 0x7073U -#define MASK_CSRRCI 0x707fU -#define MATCH_FADD_S 0x53U -#define MASK_FADD_S 0xfe00007fU -#define MATCH_FSUB_S 0x8000053U -#define MASK_FSUB_S 0xfe00007fU -#define MATCH_FMUL_S 0x10000053U -#define MASK_FMUL_S 0xfe00007fU -#define MATCH_FDIV_S 0x18000053U -#define MASK_FDIV_S 0xfe00007fU -#define MATCH_FSGNJ_S 0x20000053U -#define MASK_FSGNJ_S 0xfe00707fU -#define MATCH_FSGNJN_S 0x20001053U -#define MASK_FSGNJN_S 0xfe00707fU -#define MATCH_FSGNJX_S 0x20002053U -#define MASK_FSGNJX_S 0xfe00707fU -#define MATCH_FMIN_S 0x28000053U -#define MASK_FMIN_S 0xfe00707fU -#define MATCH_FMAX_S 0x28001053U -#define MASK_FMAX_S 0xfe00707fU -#define MATCH_FSQRT_S 0x58000053U -#define MASK_FSQRT_S 0xfff0007fU -#define MATCH_FADD_D 0x2000053U -#define MASK_FADD_D 0xfe00007fU -#define MATCH_FSUB_D 0xa000053U -#define MASK_FSUB_D 0xfe00007fU -#define MATCH_FMUL_D 0x12000053U -#define MASK_FMUL_D 0xfe00007fU -#define MATCH_FDIV_D 0x1a000053U -#define MASK_FDIV_D 0xfe00007fU -#define MATCH_FSGNJ_D 0x22000053U -#define MASK_FSGNJ_D 0xfe00707fU -#define MATCH_FSGNJN_D 0x22001053U -#define MASK_FSGNJN_D 0xfe00707fU -#define MATCH_FSGNJX_D 0x22002053U -#define MASK_FSGNJX_D 0xfe00707fU -#define MATCH_FMIN_D 0x2a000053U -#define MASK_FMIN_D 0xfe00707fU -#define MATCH_FMAX_D 0x2a001053U -#define MASK_FMAX_D 0xfe00707fU -#define MATCH_FCVT_S_D 0x40100053U -#define MASK_FCVT_S_D 0xfff0007fU -#define MATCH_FCVT_D_S 0x42000053U -#define MASK_FCVT_D_S 0xfff0007fU -#define MATCH_FSQRT_D 0x5a000053U -#define MASK_FSQRT_D 0xfff0007fU -#define MATCH_FLE_S 0xa0000053U -#define MASK_FLE_S 0xfe00707fU -#define MATCH_FLT_S 0xa0001053U -#define MASK_FLT_S 0xfe00707fU -#define MATCH_FEQ_S 0xa0002053U -#define MASK_FEQ_S 0xfe00707fU -#define MATCH_FLE_D 0xa2000053U -#define MASK_FLE_D 0xfe00707fU -#define MATCH_FLT_D 0xa2001053U -#define MASK_FLT_D 0xfe00707fU -#define MATCH_FEQ_D 0xa2002053U -#define MASK_FEQ_D 0xfe00707fU -#define MATCH_FCVT_W_S 0xc0000053U -#define MASK_FCVT_W_S 0xfff0007fU -#define MATCH_FCVT_WU_S 0xc0100053U -#define MASK_FCVT_WU_S 0xfff0007fU -#define MATCH_FCVT_L_S 0xc0200053U -#define MASK_FCVT_L_S 0xfff0007fU -#define MATCH_FCVT_LU_S 0xc0300053U -#define MASK_FCVT_LU_S 0xfff0007fU -#define MATCH_FMV_X_S 0xe0000053U -#define MASK_FMV_X_S 0xfff0707fU -#define MATCH_FCLASS_S 0xe0001053U -#define MASK_FCLASS_S 0xfff0707fU -#define MATCH_FCVT_W_D 0xc2000053U -#define MASK_FCVT_W_D 0xfff0007fU -#define MATCH_FCVT_WU_D 0xc2100053U -#define MASK_FCVT_WU_D 0xfff0007fU -#define MATCH_FCVT_L_D 0xc2200053U -#define MASK_FCVT_L_D 0xfff0007fU -#define MATCH_FCVT_LU_D 0xc2300053U -#define MASK_FCVT_LU_D 0xfff0007fU -#define MATCH_FMV_X_D 0xe2000053U -#define MASK_FMV_X_D 0xfff0707fU -#define MATCH_FCLASS_D 0xe2001053U -#define MASK_FCLASS_D 0xfff0707fU -#define MATCH_FCVT_S_W 0xd0000053U -#define MASK_FCVT_S_W 0xfff0007fU -#define MATCH_FCVT_S_WU 0xd0100053U -#define MASK_FCVT_S_WU 0xfff0007fU -#define MATCH_FCVT_S_L 0xd0200053U -#define MASK_FCVT_S_L 0xfff0007fU -#define MATCH_FCVT_S_LU 0xd0300053U -#define MASK_FCVT_S_LU 0xfff0007fU -#define MATCH_FMV_S_X 0xf0000053U -#define MASK_FMV_S_X 0xfff0707fU -#define MATCH_FCVT_D_W 0xd2000053U -#define MASK_FCVT_D_W 0xfff0007fU -#define MATCH_FCVT_D_WU 0xd2100053U -#define MASK_FCVT_D_WU 0xfff0007fU -#define MATCH_FCVT_D_L 0xd2200053U -#define MASK_FCVT_D_L 0xfff0007fU -#define MATCH_FCVT_D_LU 0xd2300053U -#define MASK_FCVT_D_LU 0xfff0007fU -#define MATCH_FMV_D_X 0xf2000053U -#define MASK_FMV_D_X 0xfff0707fU -#define MATCH_FLW 0x2007U -#define MASK_FLW 0x707fU -#define MATCH_FLD 0x3007U -#define MASK_FLD 0x707fU -#define MATCH_FSW 0x2027U -#define MASK_FSW 0x707fU -#define MATCH_FSD 0x3027U -#define MASK_FSD 0x707fU -#define MATCH_FMADD_S 0x43U -#define MASK_FMADD_S 0x600007fU -#define MATCH_FMSUB_S 0x47U -#define MASK_FMSUB_S 0x600007fU -#define MATCH_FNMSUB_S 0x4bU -#define MASK_FNMSUB_S 0x600007fU -#define MATCH_FNMADD_S 0x4fU -#define MASK_FNMADD_S 0x600007fU -#define MATCH_FMADD_D 0x2000043U -#define MASK_FMADD_D 0x600007fU -#define MATCH_FMSUB_D 0x2000047U -#define MASK_FMSUB_D 0x600007fU -#define MATCH_FNMSUB_D 0x200004bU -#define MASK_FNMSUB_D 0x600007fU -#define MATCH_FNMADD_D 0x200004fU -#define MASK_FNMADD_D 0x600007fU -#define MATCH_C_NOP 0x1U -#define MASK_C_NOP 0xffffU -#define MATCH_C_ADDI16SP 0x6101U -#define MASK_C_ADDI16SP 0xef83U -#define MATCH_C_JR 0x8002U -#define MASK_C_JR 0xf07fU -#define MATCH_C_JALR 0x9002U -#define MASK_C_JALR 0xf07fU -#define MATCH_C_EBREAK 0x9002U -#define MASK_C_EBREAK 0xffffU -#define MATCH_C_LD 0x6000U -#define MASK_C_LD 0xe003U -#define MATCH_C_SD 0xe000U -#define MASK_C_SD 0xe003U -#define MATCH_C_ADDIW 0x2001U -#define MASK_C_ADDIW 0xe003U -#define MATCH_C_LDSP 0x6002U -#define MASK_C_LDSP 0xe003U -#define MATCH_C_SDSP 0xe002U -#define MASK_C_SDSP 0xe003U -#define MATCH_C_ADDI4SPN 0x0U -#define MASK_C_ADDI4SPN 0xe003U -#define MATCH_C_FLD 0x2000U -#define MASK_C_FLD 0xe003U -#define MATCH_C_LW 0x4000U -#define MASK_C_LW 0xe003U -#define MATCH_C_FLW 0x6000U -#define MASK_C_FLW 0xe003U -#define MATCH_C_FSD 0xa000U -#define MASK_C_FSD 0xe003U -#define MATCH_C_SW 0xc000U -#define MASK_C_SW 0xe003U -#define MATCH_C_FSW 0xe000U -#define MASK_C_FSW 0xe003U -#define MATCH_C_ADDI 0x1U -#define MASK_C_ADDI 0xe003U -#define MATCH_C_JAL 0x2001U -#define MASK_C_JAL 0xe003U -#define MATCH_C_LI 0x4001U -#define MASK_C_LI 0xe003U -#define MATCH_C_LUI 0x6001U -#define MASK_C_LUI 0xe003U -#define MATCH_C_SRLI 0x8001U -#define MASK_C_SRLI 0xec03U -#define MATCH_C_SRAI 0x8401U -#define MASK_C_SRAI 0xec03U -#define MATCH_C_ANDI 0x8801U -#define MASK_C_ANDI 0xec03U -#define MATCH_C_SUB 0x8c01U -#define MASK_C_SUB 0xfc63U -#define MATCH_C_XOR 0x8c21U -#define MASK_C_XOR 0xfc63U -#define MATCH_C_OR 0x8c41U -#define MASK_C_OR 0xfc63U -#define MATCH_C_AND 0x8c61U -#define MASK_C_AND 0xfc63U -#define MATCH_C_SUBW 0x9c01U -#define MASK_C_SUBW 0xfc63U -#define MATCH_C_ADDW 0x9c21U -#define MASK_C_ADDW 0xfc63U -#define MATCH_C_J 0xa001U -#define MASK_C_J 0xe003U -#define MATCH_C_BEQZ 0xc001U -#define MASK_C_BEQZ 0xe003U -#define MATCH_C_BNEZ 0xe001U -#define MASK_C_BNEZ 0xe003U -#define MATCH_C_SLLI 0x2U -#define MASK_C_SLLI 0xe003U -#define MATCH_C_FLDSP 0x2002U -#define MASK_C_FLDSP 0xe003U -#define MATCH_C_LWSP 0x4002U -#define MASK_C_LWSP 0xe003U -#define MATCH_C_FLWSP 0x6002U -#define MASK_C_FLWSP 0xe003U -#define MATCH_C_MV 0x8002U -#define MASK_C_MV 0xf003U -#define MATCH_C_ADD 0x9002U -#define MASK_C_ADD 0xf003U -#define MATCH_C_FSDSP 0xa002U -#define MASK_C_FSDSP 0xe003U -#define MATCH_C_SWSP 0xc002U -#define MASK_C_SWSP 0xe003U -#define MATCH_C_FSWSP 0xe002U -#define MASK_C_FSWSP 0xe003U -#define MATCH_CUSTOM0 0xbU -#define MASK_CUSTOM0 0x707fU -#define MATCH_CUSTOM0_RS1 0x200bU -#define MASK_CUSTOM0_RS1 0x707fU -#define MATCH_CUSTOM0_RS1_RS2 0x300bU -#define MASK_CUSTOM0_RS1_RS2 0x707fU -#define MATCH_CUSTOM0_RD 0x400bU -#define MASK_CUSTOM0_RD 0x707fU -#define MATCH_CUSTOM0_RD_RS1 0x600bU -#define MASK_CUSTOM0_RD_RS1 0x707fU -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700bU -#define MASK_CUSTOM0_RD_RS1_RS2 0x707fU -#define MATCH_CUSTOM1 0x2bU -#define MASK_CUSTOM1 0x707fU -#define MATCH_CUSTOM1_RS1 0x202bU -#define MASK_CUSTOM1_RS1 0x707fU -#define MATCH_CUSTOM1_RS1_RS2 0x302bU -#define MASK_CUSTOM1_RS1_RS2 0x707fU -#define MATCH_CUSTOM1_RD 0x402bU -#define MASK_CUSTOM1_RD 0x707fU -#define MATCH_CUSTOM1_RD_RS1 0x602bU -#define MASK_CUSTOM1_RD_RS1 0x707fU -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702bU -#define MASK_CUSTOM1_RD_RS1_RS2 0x707fU -#define MATCH_CUSTOM2 0x5bU -#define MASK_CUSTOM2 0x707fU -#define MATCH_CUSTOM2_RS1 0x205bU -#define MASK_CUSTOM2_RS1 0x707fU -#define MATCH_CUSTOM2_RS1_RS2 0x305bU -#define MASK_CUSTOM2_RS1_RS2 0x707fU -#define MATCH_CUSTOM2_RD 0x405bU -#define MASK_CUSTOM2_RD 0x707fU -#define MATCH_CUSTOM2_RD_RS1 0x605bU -#define MASK_CUSTOM2_RD_RS1 0x707fU -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705bU -#define MASK_CUSTOM2_RD_RS1_RS2 0x707fU -#define MATCH_CUSTOM3 0x7bU -#define MASK_CUSTOM3 0x707fU -#define MATCH_CUSTOM3_RS1 0x207bU -#define MASK_CUSTOM3_RS1 0x707fU -#define MATCH_CUSTOM3_RS1_RS2 0x307bU -#define MASK_CUSTOM3_RS1_RS2 0x707fU -#define MATCH_CUSTOM3_RD 0x407bU -#define MASK_CUSTOM3_RD 0x707fU -#define MATCH_CUSTOM3_RD_RS1 0x607bU -#define MASK_CUSTOM3_RD_RS1 0x707fU -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707bU -#define MASK_CUSTOM3_RD_RS1_RS2 0x707fU -#define CSR_FFLAGS 0x1U -#define CSR_FRM 0x2U -#define CSR_FCSR 0x3U -#define CSR_CYCLE 0xc00U -#define CSR_TIME 0xc01U -#define CSR_INSTRET 0xc02U -#define CSR_HPMCOUNTER3 0xc03U -#define CSR_HPMCOUNTER4 0xc04U -#define CSR_HPMCOUNTER5 0xc05U -#define CSR_HPMCOUNTER6 0xc06U -#define CSR_HPMCOUNTER7 0xc07U -#define CSR_HPMCOUNTER8 0xc08U -#define CSR_HPMCOUNTER9 0xc09U -#define CSR_HPMCOUNTER10 0xc0aU -#define CSR_HPMCOUNTER11 0xc0bU -#define CSR_HPMCOUNTER12 0xc0cU -#define CSR_HPMCOUNTER13 0xc0dU -#define CSR_HPMCOUNTER14 0xc0eU -#define CSR_HPMCOUNTER15 0xc0fU -#define CSR_HPMCOUNTER16 0xc10U -#define CSR_HPMCOUNTER17 0xc11U -#define CSR_HPMCOUNTER18 0xc12U -#define CSR_HPMCOUNTER19 0xc13U -#define CSR_HPMCOUNTER20 0xc14U -#define CSR_HPMCOUNTER21 0xc15U -#define CSR_HPMCOUNTER22 0xc16U -#define CSR_HPMCOUNTER23 0xc17U -#define CSR_HPMCOUNTER24 0xc18U -#define CSR_HPMCOUNTER25 0xc19U -#define CSR_HPMCOUNTER26 0xc1aU -#define CSR_HPMCOUNTER27 0xc1bU -#define CSR_HPMCOUNTER28 0xc1cU -#define CSR_HPMCOUNTER29 0xc1dU -#define CSR_HPMCOUNTER30 0xc1eU -#define CSR_HPMCOUNTER31 0xc1fU -#define CSR_SSTATUS 0x100U -#define CSR_SIE 0x104U -#define CSR_STVEC 0x105U -#define CSR_SSCRATCH 0x140U -#define CSR_SEPC 0x141U -#define CSR_SCAUSE 0x142U -#define CSR_SBADADDR 0x143U -#define CSR_SIP 0x144U -#define CSR_SPTBR 0x180U -#define CSR_MSTATUS 0x300U -#define CSR_MISA 0x301U -#define CSR_MEDELEG 0x302U -#define CSR_MIDELEG 0x303U -#define CSR_MIE 0x304U -#define CSR_MTVEC 0x305U -#define CSR_MSCRATCH 0x340U -#define CSR_MEPC 0x341U -#define CSR_MCAUSE 0x342U -#define CSR_MBADADDR 0x343U -#define CSR_MIP 0x344U -#define CSR_TSELECT 0x7a0U -#define CSR_TDATA1 0x7a1U -#define CSR_TDATA2 0x7a2U -#define CSR_TDATA3 0x7a3U -#define CSR_DCSR 0x7b0U -#define CSR_DPC 0x7b1U -#define CSR_DSCRATCH 0x7b2U -#define CSR_MCYCLE 0xb00U -#define CSR_MINSTRET 0xb02U -#define CSR_MHPMCOUNTER3 0xb03U -#define CSR_MHPMCOUNTER4 0xb04U -#define CSR_MHPMCOUNTER5 0xb05U -#define CSR_MHPMCOUNTER6 0xb06U -#define CSR_MHPMCOUNTER7 0xb07U -#define CSR_MHPMCOUNTER8 0xb08U -#define CSR_MHPMCOUNTER9 0xb09U -#define CSR_MHPMCOUNTER10 0xb0aU -#define CSR_MHPMCOUNTER11 0xb0bU -#define CSR_MHPMCOUNTER12 0xb0cU -#define CSR_MHPMCOUNTER13 0xb0dU -#define CSR_MHPMCOUNTER14 0xb0eU -#define CSR_MHPMCOUNTER15 0xb0fU -#define CSR_MHPMCOUNTER16 0xb10U -#define CSR_MHPMCOUNTER17 0xb11U -#define CSR_MHPMCOUNTER18 0xb12U -#define CSR_MHPMCOUNTER19 0xb13U -#define CSR_MHPMCOUNTER20 0xb14U -#define CSR_MHPMCOUNTER21 0xb15U -#define CSR_MHPMCOUNTER22 0xb16U -#define CSR_MHPMCOUNTER23 0xb17U -#define CSR_MHPMCOUNTER24 0xb18U -#define CSR_MHPMCOUNTER25 0xb19U -#define CSR_MHPMCOUNTER26 0xb1aU -#define CSR_MHPMCOUNTER27 0xb1bU -#define CSR_MHPMCOUNTER28 0xb1cU -#define CSR_MHPMCOUNTER29 0xb1dU -#define CSR_MHPMCOUNTER30 0xb1eU -#define CSR_MHPMCOUNTER31 0xb1fU -#define CSR_MUCOUNTEREN 0x320U -#define CSR_MSCOUNTEREN 0x321U -#define CSR_MHPMEVENT3 0x323U -#define CSR_MHPMEVENT4 0x324U -#define CSR_MHPMEVENT5 0x325U -#define CSR_MHPMEVENT6 0x326U -#define CSR_MHPMEVENT7 0x327U -#define CSR_MHPMEVENT8 0x328U -#define CSR_MHPMEVENT9 0x329U -#define CSR_MHPMEVENT10 0x32aU -#define CSR_MHPMEVENT11 0x32bU -#define CSR_MHPMEVENT12 0x32cU -#define CSR_MHPMEVENT13 0x32dU -#define CSR_MHPMEVENT14 0x32eU -#define CSR_MHPMEVENT15 0x32fU -#define CSR_MHPMEVENT16 0x330U -#define CSR_MHPMEVENT17 0x331U -#define CSR_MHPMEVENT18 0x332U -#define CSR_MHPMEVENT19 0x333U -#define CSR_MHPMEVENT20 0x334U -#define CSR_MHPMEVENT21 0x335U -#define CSR_MHPMEVENT22 0x336U -#define CSR_MHPMEVENT23 0x337U -#define CSR_MHPMEVENT24 0x338U -#define CSR_MHPMEVENT25 0x339U -#define CSR_MHPMEVENT26 0x33aU -#define CSR_MHPMEVENT27 0x33bU -#define CSR_MHPMEVENT28 0x33cU -#define CSR_MHPMEVENT29 0x33dU -#define CSR_MHPMEVENT30 0x33eU -#define CSR_MHPMEVENT31 0x33fU -#define CSR_MVENDORID 0xf11U -#define CSR_MARCHID 0xf12U -#define CSR_MIMPID 0xf13U -#define CSR_MHARTID 0xf14U -#define CSR_CYCLEH 0xc80U -#define CSR_TIMEH 0xc81U -#define CSR_INSTRETH 0xc82U -#define CSR_HPMCOUNTER3H 0xc83U -#define CSR_HPMCOUNTER4H 0xc84U -#define CSR_HPMCOUNTER5H 0xc85U -#define CSR_HPMCOUNTER6H 0xc86U -#define CSR_HPMCOUNTER7H 0xc87U -#define CSR_HPMCOUNTER8H 0xc88U -#define CSR_HPMCOUNTER9H 0xc89U -#define CSR_HPMCOUNTER10H 0xc8aU -#define CSR_HPMCOUNTER11H 0xc8bU -#define CSR_HPMCOUNTER12H 0xc8cU -#define CSR_HPMCOUNTER13H 0xc8dU -#define CSR_HPMCOUNTER14H 0xc8eU -#define CSR_HPMCOUNTER15H 0xc8fU -#define CSR_HPMCOUNTER16H 0xc90U -#define CSR_HPMCOUNTER17H 0xc91U -#define CSR_HPMCOUNTER18H 0xc92U -#define CSR_HPMCOUNTER19H 0xc93U -#define CSR_HPMCOUNTER20H 0xc94U -#define CSR_HPMCOUNTER21H 0xc95U -#define CSR_HPMCOUNTER22H 0xc96U -#define CSR_HPMCOUNTER23H 0xc97U -#define CSR_HPMCOUNTER24H 0xc98U -#define CSR_HPMCOUNTER25H 0xc99U -#define CSR_HPMCOUNTER26H 0xc9aU -#define CSR_HPMCOUNTER27H 0xc9bU -#define CSR_HPMCOUNTER28H 0xc9cU -#define CSR_HPMCOUNTER29H 0xc9dU -#define CSR_HPMCOUNTER30H 0xc9eU -#define CSR_HPMCOUNTER31H 0xc9fU -#define CSR_MCYCLEH 0xb80U -#define CSR_MINSTRETH 0xb82U -#define CSR_MHPMCOUNTER3H 0xb83U -#define CSR_MHPMCOUNTER4H 0xb84U -#define CSR_MHPMCOUNTER5H 0xb85U -#define CSR_MHPMCOUNTER6H 0xb86U -#define CSR_MHPMCOUNTER7H 0xb87U -#define CSR_MHPMCOUNTER8H 0xb88U -#define CSR_MHPMCOUNTER9H 0xb89U -#define CSR_MHPMCOUNTER10H 0xb8aU -#define CSR_MHPMCOUNTER11H 0xb8bU -#define CSR_MHPMCOUNTER12H 0xb8cU -#define CSR_MHPMCOUNTER13H 0xb8dU -#define CSR_MHPMCOUNTER14H 0xb8eU -#define CSR_MHPMCOUNTER15H 0xb8fU -#define CSR_MHPMCOUNTER16H 0xb90U -#define CSR_MHPMCOUNTER17H 0xb91U -#define CSR_MHPMCOUNTER18H 0xb92U -#define CSR_MHPMCOUNTER19H 0xb93U -#define CSR_MHPMCOUNTER20H 0xb94U -#define CSR_MHPMCOUNTER21H 0xb95U -#define CSR_MHPMCOUNTER22H 0xb96U -#define CSR_MHPMCOUNTER23H 0xb97U -#define CSR_MHPMCOUNTER24H 0xb98U -#define CSR_MHPMCOUNTER25H 0xb99U -#define CSR_MHPMCOUNTER26H 0xb9aU -#define CSR_MHPMCOUNTER27H 0xb9bU -#define CSR_MHPMCOUNTER28H 0xb9cU -#define CSR_MHPMCOUNTER29H 0xb9dU -#define CSR_MHPMCOUNTER30H 0xb9eU -#define CSR_MHPMCOUNTER31H 0xb9fU -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#endif -#if defined(DECLARE_INSN) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif -#if defined(DECLARE_CSR) -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#if defined(DECLARE_CAUSE) -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -#endif diff --git a/Kboot/src/bootloader_hi/include/fpioa.h b/Kboot/src/bootloader_hi/include/fpioa.h deleted file mode 100644 index c602ae9..0000000 --- a/Kboot/src/bootloader_hi/include/fpioa.h +++ /dev/null @@ -1,1035 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/** - * @file - * @brief Field Programmable GPIO Array (FPIOA) - * - * The FPIOA peripheral supports the following features: - * - * - 48 IO with 256 functions - * - * - Schmitt trigger - * - * - Invert input and output - * - * - Pull up and pull down - * - * - Driving selector - * - * - Static input and output - * - */ - -#ifndef _DRIVER_FPIOA_H -#define _DRIVER_FPIOA_H - -#include -#include "platform.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* clang-format off */ -/* Pad number settings */ -#define FPIOA_NUM_IO (48) -/* clang-format on */ - -/** - * @brief FPIOA IO functions - * - * @note FPIOA pin function table - * - * | Function | Name | Description | - * |-----------|------------------|-----------------------------------| - * | 0 | JTAG_TCLK | JTAG Test Clock | - * | 1 | JTAG_TDI | JTAG Test Data In | - * | 2 | JTAG_TMS | JTAG Test Mode Select | - * | 3 | JTAG_TDO | JTAG Test Data Out | - * | 4 | SPI0_D0 | SPI0 Data 0 | - * | 5 | SPI0_D1 | SPI0 Data 1 | - * | 6 | SPI0_D2 | SPI0 Data 2 | - * | 7 | SPI0_D3 | SPI0 Data 3 | - * | 8 | SPI0_D4 | SPI0 Data 4 | - * | 9 | SPI0_D5 | SPI0 Data 5 | - * | 10 | SPI0_D6 | SPI0 Data 6 | - * | 11 | SPI0_D7 | SPI0 Data 7 | - * | 12 | SPI0_SS0 | SPI0 Chip Select 0 | - * | 13 | SPI0_SS1 | SPI0 Chip Select 1 | - * | 14 | SPI0_SS2 | SPI0 Chip Select 2 | - * | 15 | SPI0_SS3 | SPI0 Chip Select 3 | - * | 16 | SPI0_ARB | SPI0 Arbitration | - * | 17 | SPI0_SCLK | SPI0 Serial Clock | - * | 18 | UARTHS_RX | UART High speed Receiver | - * | 19 | UARTHS_TX | UART High speed Transmitter | - * | 20 | RESV6 | Reserved function | - * | 21 | RESV7 | Reserved function | - * | 22 | CLK_SPI1 | Clock SPI1 | - * | 23 | CLK_I2C1 | Clock I2C1 | - * | 24 | GPIOHS0 | GPIO High speed 0 | - * | 25 | GPIOHS1 | GPIO High speed 1 | - * | 26 | GPIOHS2 | GPIO High speed 2 | - * | 27 | GPIOHS3 | GPIO High speed 3 | - * | 28 | GPIOHS4 | GPIO High speed 4 | - * | 29 | GPIOHS5 | GPIO High speed 5 | - * | 30 | GPIOHS6 | GPIO High speed 6 | - * | 31 | GPIOHS7 | GPIO High speed 7 | - * | 32 | GPIOHS8 | GPIO High speed 8 | - * | 33 | GPIOHS9 | GPIO High speed 9 | - * | 34 | GPIOHS10 | GPIO High speed 10 | - * | 35 | GPIOHS11 | GPIO High speed 11 | - * | 36 | GPIOHS12 | GPIO High speed 12 | - * | 37 | GPIOHS13 | GPIO High speed 13 | - * | 38 | GPIOHS14 | GPIO High speed 14 | - * | 39 | GPIOHS15 | GPIO High speed 15 | - * | 40 | GPIOHS16 | GPIO High speed 16 | - * | 41 | GPIOHS17 | GPIO High speed 17 | - * | 42 | GPIOHS18 | GPIO High speed 18 | - * | 43 | GPIOHS19 | GPIO High speed 19 | - * | 44 | GPIOHS20 | GPIO High speed 20 | - * | 45 | GPIOHS21 | GPIO High speed 21 | - * | 46 | GPIOHS22 | GPIO High speed 22 | - * | 47 | GPIOHS23 | GPIO High speed 23 | - * | 48 | GPIOHS24 | GPIO High speed 24 | - * | 49 | GPIOHS25 | GPIO High speed 25 | - * | 50 | GPIOHS26 | GPIO High speed 26 | - * | 51 | GPIOHS27 | GPIO High speed 27 | - * | 52 | GPIOHS28 | GPIO High speed 28 | - * | 53 | GPIOHS29 | GPIO High speed 29 | - * | 54 | GPIOHS30 | GPIO High speed 30 | - * | 55 | GPIOHS31 | GPIO High speed 31 | - * | 56 | GPIO0 | GPIO pin 0 | - * | 57 | GPIO1 | GPIO pin 1 | - * | 58 | GPIO2 | GPIO pin 2 | - * | 59 | GPIO3 | GPIO pin 3 | - * | 60 | GPIO4 | GPIO pin 4 | - * | 61 | GPIO5 | GPIO pin 5 | - * | 62 | GPIO6 | GPIO pin 6 | - * | 63 | GPIO7 | GPIO pin 7 | - * | 64 | UART1_RX | UART1 Receiver | - * | 65 | UART1_TX | UART1 Transmitter | - * | 66 | UART2_RX | UART2 Receiver | - * | 67 | UART2_TX | UART2 Transmitter | - * | 68 | UART3_RX | UART3 Receiver | - * | 69 | UART3_TX | UART3 Transmitter | - * | 70 | SPI1_D0 | SPI1 Data 0 | - * | 71 | SPI1_D1 | SPI1 Data 1 | - * | 72 | SPI1_D2 | SPI1 Data 2 | - * | 73 | SPI1_D3 | SPI1 Data 3 | - * | 74 | SPI1_D4 | SPI1 Data 4 | - * | 75 | SPI1_D5 | SPI1 Data 5 | - * | 76 | SPI1_D6 | SPI1 Data 6 | - * | 77 | SPI1_D7 | SPI1 Data 7 | - * | 78 | SPI1_SS0 | SPI1 Chip Select 0 | - * | 79 | SPI1_SS1 | SPI1 Chip Select 1 | - * | 80 | SPI1_SS2 | SPI1 Chip Select 2 | - * | 81 | SPI1_SS3 | SPI1 Chip Select 3 | - * | 82 | SPI1_ARB | SPI1 Arbitration | - * | 83 | SPI1_SCLK | SPI1 Serial Clock | - * | 84 | SPI_SLAVE_D0 | SPI Slave Data 0 | - * | 85 | SPI_SLAVE_SS | SPI Slave Select | - * | 86 | SPI_SLAVE_SCLK | SPI Slave Serial Clock | - * | 87 | I2S0_MCLK | I2S0 Master Clock | - * | 88 | I2S0_SCLK | I2S0 Serial Clock(BCLK) | - * | 89 | I2S0_WS | I2S0 Word Select(LRCLK) | - * | 90 | I2S0_IN_D0 | I2S0 Serial Data Input 0 | - * | 91 | I2S0_IN_D1 | I2S0 Serial Data Input 1 | - * | 92 | I2S0_IN_D2 | I2S0 Serial Data Input 2 | - * | 93 | I2S0_IN_D3 | I2S0 Serial Data Input 3 | - * | 94 | I2S0_OUT_D0 | I2S0 Serial Data Output 0 | - * | 95 | I2S0_OUT_D1 | I2S0 Serial Data Output 1 | - * | 96 | I2S0_OUT_D2 | I2S0 Serial Data Output 2 | - * | 97 | I2S0_OUT_D3 | I2S0 Serial Data Output 3 | - * | 98 | I2S1_MCLK | I2S1 Master Clock | - * | 99 | I2S1_SCLK | I2S1 Serial Clock(BCLK) | - * | 100 | I2S1_WS | I2S1 Word Select(LRCLK) | - * | 101 | I2S1_IN_D0 | I2S1 Serial Data Input 0 | - * | 102 | I2S1_IN_D1 | I2S1 Serial Data Input 1 | - * | 103 | I2S1_IN_D2 | I2S1 Serial Data Input 2 | - * | 104 | I2S1_IN_D3 | I2S1 Serial Data Input 3 | - * | 105 | I2S1_OUT_D0 | I2S1 Serial Data Output 0 | - * | 106 | I2S1_OUT_D1 | I2S1 Serial Data Output 1 | - * | 107 | I2S1_OUT_D2 | I2S1 Serial Data Output 2 | - * | 108 | I2S1_OUT_D3 | I2S1 Serial Data Output 3 | - * | 109 | I2S2_MCLK | I2S2 Master Clock | - * | 110 | I2S2_SCLK | I2S2 Serial Clock(BCLK) | - * | 111 | I2S2_WS | I2S2 Word Select(LRCLK) | - * | 112 | I2S2_IN_D0 | I2S2 Serial Data Input 0 | - * | 113 | I2S2_IN_D1 | I2S2 Serial Data Input 1 | - * | 114 | I2S2_IN_D2 | I2S2 Serial Data Input 2 | - * | 115 | I2S2_IN_D3 | I2S2 Serial Data Input 3 | - * | 116 | I2S2_OUT_D0 | I2S2 Serial Data Output 0 | - * | 117 | I2S2_OUT_D1 | I2S2 Serial Data Output 1 | - * | 118 | I2S2_OUT_D2 | I2S2 Serial Data Output 2 | - * | 119 | I2S2_OUT_D3 | I2S2 Serial Data Output 3 | - * | 120 | RESV0 | Reserved function | - * | 121 | RESV1 | Reserved function | - * | 122 | RESV2 | Reserved function | - * | 123 | RESV3 | Reserved function | - * | 124 | RESV4 | Reserved function | - * | 125 | RESV5 | Reserved function | - * | 126 | I2C0_SCLK | I2C0 Serial Clock | - * | 127 | I2C0_SDA | I2C0 Serial Data | - * | 128 | I2C1_SCLK | I2C1 Serial Clock | - * | 129 | I2C1_SDA | I2C1 Serial Data | - * | 130 | I2C2_SCLK | I2C2 Serial Clock | - * | 131 | I2C2_SDA | I2C2 Serial Data | - * | 132 | CMOS_XCLK | DVP System Clock | - * | 133 | CMOS_RST | DVP System Reset | - * | 134 | CMOS_PWDN | DVP Power Down Mode | - * | 135 | CMOS_VSYNC | DVP Vertical Sync | - * | 136 | CMOS_HREF | DVP Horizontal Reference output | - * | 137 | CMOS_PCLK | Pixel Clock | - * | 138 | CMOS_D0 | Data Bit 0 | - * | 139 | CMOS_D1 | Data Bit 1 | - * | 140 | CMOS_D2 | Data Bit 2 | - * | 141 | CMOS_D3 | Data Bit 3 | - * | 142 | CMOS_D4 | Data Bit 4 | - * | 143 | CMOS_D5 | Data Bit 5 | - * | 144 | CMOS_D6 | Data Bit 6 | - * | 145 | CMOS_D7 | Data Bit 7 | - * | 146 | SCCB_SCLK | SCCB Serial Clock | - * | 147 | SCCB_SDA | SCCB Serial Data | - * | 148 | UART1_CTS | UART1 Clear To Send | - * | 149 | UART1_DSR | UART1 Data Set Ready | - * | 150 | UART1_DCD | UART1 Data Carrier Detect | - * | 151 | UART1_RI | UART1 Ring Indicator | - * | 152 | UART1_SIR_IN | UART1 Serial Infrared Input | - * | 153 | UART1_DTR | UART1 Data Terminal Ready | - * | 154 | UART1_RTS | UART1 Request To Send | - * | 155 | UART1_OUT2 | UART1 User-designated Output 2 | - * | 156 | UART1_OUT1 | UART1 User-designated Output 1 | - * | 157 | UART1_SIR_OUT | UART1 Serial Infrared Output | - * | 158 | UART1_BAUD | UART1 Transmit Clock Output | - * | 159 | UART1_RE | UART1 Receiver Output Enable | - * | 160 | UART1_DE | UART1 Driver Output Enable | - * | 161 | UART1_RS485_EN | UART1 RS485 Enable | - * | 162 | UART2_CTS | UART2 Clear To Send | - * | 163 | UART2_DSR | UART2 Data Set Ready | - * | 164 | UART2_DCD | UART2 Data Carrier Detect | - * | 165 | UART2_RI | UART2 Ring Indicator | - * | 166 | UART2_SIR_IN | UART2 Serial Infrared Input | - * | 167 | UART2_DTR | UART2 Data Terminal Ready | - * | 168 | UART2_RTS | UART2 Request To Send | - * | 169 | UART2_OUT2 | UART2 User-designated Output 2 | - * | 170 | UART2_OUT1 | UART2 User-designated Output 1 | - * | 171 | UART2_SIR_OUT | UART2 Serial Infrared Output | - * | 172 | UART2_BAUD | UART2 Transmit Clock Output | - * | 173 | UART2_RE | UART2 Receiver Output Enable | - * | 174 | UART2_DE | UART2 Driver Output Enable | - * | 175 | UART2_RS485_EN | UART2 RS485 Enable | - * | 176 | UART3_CTS | UART3 Clear To Send | - * | 177 | UART3_DSR | UART3 Data Set Ready | - * | 178 | UART3_DCD | UART3 Data Carrier Detect | - * | 179 | UART3_RI | UART3 Ring Indicator | - * | 180 | UART3_SIR_IN | UART3 Serial Infrared Input | - * | 181 | UART3_DTR | UART3 Data Terminal Ready | - * | 182 | UART3_RTS | UART3 Request To Send | - * | 183 | UART3_OUT2 | UART3 User-designated Output 2 | - * | 184 | UART3_OUT1 | UART3 User-designated Output 1 | - * | 185 | UART3_SIR_OUT | UART3 Serial Infrared Output | - * | 186 | UART3_BAUD | UART3 Transmit Clock Output | - * | 187 | UART3_RE | UART3 Receiver Output Enable | - * | 188 | UART3_DE | UART3 Driver Output Enable | - * | 189 | UART3_RS485_EN | UART3 RS485 Enable | - * | 190 | TIMER0_TOGGLE1 | TIMER0 Toggle Output 1 | - * | 191 | TIMER0_TOGGLE2 | TIMER0 Toggle Output 2 | - * | 192 | TIMER0_TOGGLE3 | TIMER0 Toggle Output 3 | - * | 193 | TIMER0_TOGGLE4 | TIMER0 Toggle Output 4 | - * | 194 | TIMER1_TOGGLE1 | TIMER1 Toggle Output 1 | - * | 195 | TIMER1_TOGGLE2 | TIMER1 Toggle Output 2 | - * | 196 | TIMER1_TOGGLE3 | TIMER1 Toggle Output 3 | - * | 197 | TIMER1_TOGGLE4 | TIMER1 Toggle Output 4 | - * | 198 | TIMER2_TOGGLE1 | TIMER2 Toggle Output 1 | - * | 199 | TIMER2_TOGGLE2 | TIMER2 Toggle Output 2 | - * | 200 | TIMER2_TOGGLE3 | TIMER2 Toggle Output 3 | - * | 201 | TIMER2_TOGGLE4 | TIMER2 Toggle Output 4 | - * | 202 | CLK_SPI2 | Clock SPI2 | - * | 203 | CLK_I2C2 | Clock I2C2 | - * | 204 | INTERNAL0 | Internal function signal 0 | - * | 205 | INTERNAL1 | Internal function signal 1 | - * | 206 | INTERNAL2 | Internal function signal 2 | - * | 207 | INTERNAL3 | Internal function signal 3 | - * | 208 | INTERNAL4 | Internal function signal 4 | - * | 209 | INTERNAL5 | Internal function signal 5 | - * | 210 | INTERNAL6 | Internal function signal 6 | - * | 211 | INTERNAL7 | Internal function signal 7 | - * | 212 | INTERNAL8 | Internal function signal 8 | - * | 213 | INTERNAL9 | Internal function signal 9 | - * | 214 | INTERNAL10 | Internal function signal 10 | - * | 215 | INTERNAL11 | Internal function signal 11 | - * | 216 | INTERNAL12 | Internal function signal 12 | - * | 217 | INTERNAL13 | Internal function signal 13 | - * | 218 | INTERNAL14 | Internal function signal 14 | - * | 219 | INTERNAL15 | Internal function signal 15 | - * | 220 | INTERNAL16 | Internal function signal 16 | - * | 221 | INTERNAL17 | Internal function signal 17 | - * | 222 | CONSTANT | Constant function | - * | 223 | INTERNAL18 | Internal function signal 18 | - * | 224 | DEBUG0 | Debug function 0 | - * | 225 | DEBUG1 | Debug function 1 | - * | 226 | DEBUG2 | Debug function 2 | - * | 227 | DEBUG3 | Debug function 3 | - * | 228 | DEBUG4 | Debug function 4 | - * | 229 | DEBUG5 | Debug function 5 | - * | 230 | DEBUG6 | Debug function 6 | - * | 231 | DEBUG7 | Debug function 7 | - * | 232 | DEBUG8 | Debug function 8 | - * | 233 | DEBUG9 | Debug function 9 | - * | 234 | DEBUG10 | Debug function 10 | - * | 235 | DEBUG11 | Debug function 11 | - * | 236 | DEBUG12 | Debug function 12 | - * | 237 | DEBUG13 | Debug function 13 | - * | 238 | DEBUG14 | Debug function 14 | - * | 239 | DEBUG15 | Debug function 15 | - * | 240 | DEBUG16 | Debug function 16 | - * | 241 | DEBUG17 | Debug function 17 | - * | 242 | DEBUG18 | Debug function 18 | - * | 243 | DEBUG19 | Debug function 19 | - * | 244 | DEBUG20 | Debug function 20 | - * | 245 | DEBUG21 | Debug function 21 | - * | 246 | DEBUG22 | Debug function 22 | - * | 247 | DEBUG23 | Debug function 23 | - * | 248 | DEBUG24 | Debug function 24 | - * | 249 | DEBUG25 | Debug function 25 | - * | 250 | DEBUG26 | Debug function 26 | - * | 251 | DEBUG27 | Debug function 27 | - * | 252 | DEBUG28 | Debug function 28 | - * | 253 | DEBUG29 | Debug function 29 | - * | 254 | DEBUG30 | Debug function 30 | - * | 255 | DEBUG31 | Debug function 31 | - * - * Any IO of FPIOA have 256 functions, it is a IO-function matrix. - * All IO have default reset function, after reset, re-configure - * IO function is required. - */ - -/* clang-format off */ -typedef enum _fpioa_function -{ - FUNC_JTAG_TCLK = 0, /*!< JTAG Test Clock */ - FUNC_JTAG_TDI = 1, /*!< JTAG Test Data In */ - FUNC_JTAG_TMS = 2, /*!< JTAG Test Mode Select */ - FUNC_JTAG_TDO = 3, /*!< JTAG Test Data Out */ - FUNC_SPI0_D0 = 4, /*!< SPI0 Data 0 */ - FUNC_SPI0_D1 = 5, /*!< SPI0 Data 1 */ - FUNC_SPI0_D2 = 6, /*!< SPI0 Data 2 */ - FUNC_SPI0_D3 = 7, /*!< SPI0 Data 3 */ - FUNC_SPI0_D4 = 8, /*!< SPI0 Data 4 */ - FUNC_SPI0_D5 = 9, /*!< SPI0 Data 5 */ - FUNC_SPI0_D6 = 10, /*!< SPI0 Data 6 */ - FUNC_SPI0_D7 = 11, /*!< SPI0 Data 7 */ - FUNC_SPI0_SS0 = 12, /*!< SPI0 Chip Select 0 */ - FUNC_SPI0_SS1 = 13, /*!< SPI0 Chip Select 1 */ - FUNC_SPI0_SS2 = 14, /*!< SPI0 Chip Select 2 */ - FUNC_SPI0_SS3 = 15, /*!< SPI0 Chip Select 3 */ - FUNC_SPI0_ARB = 16, /*!< SPI0 Arbitration */ - FUNC_SPI0_SCLK = 17, /*!< SPI0 Serial Clock */ - FUNC_UARTHS_RX = 18, /*!< UART High speed Receiver */ - FUNC_UARTHS_TX = 19, /*!< UART High speed Transmitter */ - FUNC_RESV6 = 20, /*!< Reserved function */ - FUNC_RESV7 = 21, /*!< Reserved function */ - FUNC_CLK_SPI1 = 22, /*!< Clock SPI1 */ - FUNC_CLK_I2C1 = 23, /*!< Clock I2C1 */ - FUNC_GPIOHS0 = 24, /*!< GPIO High speed 0 */ - FUNC_GPIOHS1 = 25, /*!< GPIO High speed 1 */ - FUNC_GPIOHS2 = 26, /*!< GPIO High speed 2 */ - FUNC_GPIOHS3 = 27, /*!< GPIO High speed 3 */ - FUNC_GPIOHS4 = 28, /*!< GPIO High speed 4 */ - FUNC_GPIOHS5 = 29, /*!< GPIO High speed 5 */ - FUNC_GPIOHS6 = 30, /*!< GPIO High speed 6 */ - FUNC_GPIOHS7 = 31, /*!< GPIO High speed 7 */ - FUNC_GPIOHS8 = 32, /*!< GPIO High speed 8 */ - FUNC_GPIOHS9 = 33, /*!< GPIO High speed 9 */ - FUNC_GPIOHS10 = 34, /*!< GPIO High speed 10 */ - FUNC_GPIOHS11 = 35, /*!< GPIO High speed 11 */ - FUNC_GPIOHS12 = 36, /*!< GPIO High speed 12 */ - FUNC_GPIOHS13 = 37, /*!< GPIO High speed 13 */ - FUNC_GPIOHS14 = 38, /*!< GPIO High speed 14 */ - FUNC_GPIOHS15 = 39, /*!< GPIO High speed 15 */ - FUNC_GPIOHS16 = 40, /*!< GPIO High speed 16 */ - FUNC_GPIOHS17 = 41, /*!< GPIO High speed 17 */ - FUNC_GPIOHS18 = 42, /*!< GPIO High speed 18 */ - FUNC_GPIOHS19 = 43, /*!< GPIO High speed 19 */ - FUNC_GPIOHS20 = 44, /*!< GPIO High speed 20 */ - FUNC_GPIOHS21 = 45, /*!< GPIO High speed 21 */ - FUNC_GPIOHS22 = 46, /*!< GPIO High speed 22 */ - FUNC_GPIOHS23 = 47, /*!< GPIO High speed 23 */ - FUNC_GPIOHS24 = 48, /*!< GPIO High speed 24 */ - FUNC_GPIOHS25 = 49, /*!< GPIO High speed 25 */ - FUNC_GPIOHS26 = 50, /*!< GPIO High speed 26 */ - FUNC_GPIOHS27 = 51, /*!< GPIO High speed 27 */ - FUNC_GPIOHS28 = 52, /*!< GPIO High speed 28 */ - FUNC_GPIOHS29 = 53, /*!< GPIO High speed 29 */ - FUNC_GPIOHS30 = 54, /*!< GPIO High speed 30 */ - FUNC_GPIOHS31 = 55, /*!< GPIO High speed 31 */ - FUNC_GPIO0 = 56, /*!< GPIO pin 0 */ - FUNC_GPIO1 = 57, /*!< GPIO pin 1 */ - FUNC_GPIO2 = 58, /*!< GPIO pin 2 */ - FUNC_GPIO3 = 59, /*!< GPIO pin 3 */ - FUNC_GPIO4 = 60, /*!< GPIO pin 4 */ - FUNC_GPIO5 = 61, /*!< GPIO pin 5 */ - FUNC_GPIO6 = 62, /*!< GPIO pin 6 */ - FUNC_GPIO7 = 63, /*!< GPIO pin 7 */ - FUNC_UART1_RX = 64, /*!< UART1 Receiver */ - FUNC_UART1_TX = 65, /*!< UART1 Transmitter */ - FUNC_UART2_RX = 66, /*!< UART2 Receiver */ - FUNC_UART2_TX = 67, /*!< UART2 Transmitter */ - FUNC_UART3_RX = 68, /*!< UART3 Receiver */ - FUNC_UART3_TX = 69, /*!< UART3 Transmitter */ - FUNC_SPI1_D0 = 70, /*!< SPI1 Data 0 */ - FUNC_SPI1_D1 = 71, /*!< SPI1 Data 1 */ - FUNC_SPI1_D2 = 72, /*!< SPI1 Data 2 */ - FUNC_SPI1_D3 = 73, /*!< SPI1 Data 3 */ - FUNC_SPI1_D4 = 74, /*!< SPI1 Data 4 */ - FUNC_SPI1_D5 = 75, /*!< SPI1 Data 5 */ - FUNC_SPI1_D6 = 76, /*!< SPI1 Data 6 */ - FUNC_SPI1_D7 = 77, /*!< SPI1 Data 7 */ - FUNC_SPI1_SS0 = 78, /*!< SPI1 Chip Select 0 */ - FUNC_SPI1_SS1 = 79, /*!< SPI1 Chip Select 1 */ - FUNC_SPI1_SS2 = 80, /*!< SPI1 Chip Select 2 */ - FUNC_SPI1_SS3 = 81, /*!< SPI1 Chip Select 3 */ - FUNC_SPI1_ARB = 82, /*!< SPI1 Arbitration */ - FUNC_SPI1_SCLK = 83, /*!< SPI1 Serial Clock */ - FUNC_SPI_SLAVE_D0 = 84, /*!< SPI Slave Data 0 */ - FUNC_SPI_SLAVE_SS = 85, /*!< SPI Slave Select */ - FUNC_SPI_SLAVE_SCLK = 86, /*!< SPI Slave Serial Clock */ - FUNC_I2S0_MCLK = 87, /*!< I2S0 Master Clock */ - FUNC_I2S0_SCLK = 88, /*!< I2S0 Serial Clock(BCLK) */ - FUNC_I2S0_WS = 89, /*!< I2S0 Word Select(LRCLK) */ - FUNC_I2S0_IN_D0 = 90, /*!< I2S0 Serial Data Input 0 */ - FUNC_I2S0_IN_D1 = 91, /*!< I2S0 Serial Data Input 1 */ - FUNC_I2S0_IN_D2 = 92, /*!< I2S0 Serial Data Input 2 */ - FUNC_I2S0_IN_D3 = 93, /*!< I2S0 Serial Data Input 3 */ - FUNC_I2S0_OUT_D0 = 94, /*!< I2S0 Serial Data Output 0 */ - FUNC_I2S0_OUT_D1 = 95, /*!< I2S0 Serial Data Output 1 */ - FUNC_I2S0_OUT_D2 = 96, /*!< I2S0 Serial Data Output 2 */ - FUNC_I2S0_OUT_D3 = 97, /*!< I2S0 Serial Data Output 3 */ - FUNC_I2S1_MCLK = 98, /*!< I2S1 Master Clock */ - FUNC_I2S1_SCLK = 99, /*!< I2S1 Serial Clock(BCLK) */ - FUNC_I2S1_WS = 100, /*!< I2S1 Word Select(LRCLK) */ - FUNC_I2S1_IN_D0 = 101, /*!< I2S1 Serial Data Input 0 */ - FUNC_I2S1_IN_D1 = 102, /*!< I2S1 Serial Data Input 1 */ - FUNC_I2S1_IN_D2 = 103, /*!< I2S1 Serial Data Input 2 */ - FUNC_I2S1_IN_D3 = 104, /*!< I2S1 Serial Data Input 3 */ - FUNC_I2S1_OUT_D0 = 105, /*!< I2S1 Serial Data Output 0 */ - FUNC_I2S1_OUT_D1 = 106, /*!< I2S1 Serial Data Output 1 */ - FUNC_I2S1_OUT_D2 = 107, /*!< I2S1 Serial Data Output 2 */ - FUNC_I2S1_OUT_D3 = 108, /*!< I2S1 Serial Data Output 3 */ - FUNC_I2S2_MCLK = 109, /*!< I2S2 Master Clock */ - FUNC_I2S2_SCLK = 110, /*!< I2S2 Serial Clock(BCLK) */ - FUNC_I2S2_WS = 111, /*!< I2S2 Word Select(LRCLK) */ - FUNC_I2S2_IN_D0 = 112, /*!< I2S2 Serial Data Input 0 */ - FUNC_I2S2_IN_D1 = 113, /*!< I2S2 Serial Data Input 1 */ - FUNC_I2S2_IN_D2 = 114, /*!< I2S2 Serial Data Input 2 */ - FUNC_I2S2_IN_D3 = 115, /*!< I2S2 Serial Data Input 3 */ - FUNC_I2S2_OUT_D0 = 116, /*!< I2S2 Serial Data Output 0 */ - FUNC_I2S2_OUT_D1 = 117, /*!< I2S2 Serial Data Output 1 */ - FUNC_I2S2_OUT_D2 = 118, /*!< I2S2 Serial Data Output 2 */ - FUNC_I2S2_OUT_D3 = 119, /*!< I2S2 Serial Data Output 3 */ - FUNC_RESV0 = 120, /*!< Reserved function */ - FUNC_RESV1 = 121, /*!< Reserved function */ - FUNC_RESV2 = 122, /*!< Reserved function */ - FUNC_RESV3 = 123, /*!< Reserved function */ - FUNC_RESV4 = 124, /*!< Reserved function */ - FUNC_RESV5 = 125, /*!< Reserved function */ - FUNC_I2C0_SCLK = 126, /*!< I2C0 Serial Clock */ - FUNC_I2C0_SDA = 127, /*!< I2C0 Serial Data */ - FUNC_I2C1_SCLK = 128, /*!< I2C1 Serial Clock */ - FUNC_I2C1_SDA = 129, /*!< I2C1 Serial Data */ - FUNC_I2C2_SCLK = 130, /*!< I2C2 Serial Clock */ - FUNC_I2C2_SDA = 131, /*!< I2C2 Serial Data */ - FUNC_CMOS_XCLK = 132, /*!< DVP System Clock */ - FUNC_CMOS_RST = 133, /*!< DVP System Reset */ - FUNC_CMOS_PWDN = 134, /*!< DVP Power Down Mode */ - FUNC_CMOS_VSYNC = 135, /*!< DVP Vertical Sync */ - FUNC_CMOS_HREF = 136, /*!< DVP Horizontal Reference output */ - FUNC_CMOS_PCLK = 137, /*!< Pixel Clock */ - FUNC_CMOS_D0 = 138, /*!< Data Bit 0 */ - FUNC_CMOS_D1 = 139, /*!< Data Bit 1 */ - FUNC_CMOS_D2 = 140, /*!< Data Bit 2 */ - FUNC_CMOS_D3 = 141, /*!< Data Bit 3 */ - FUNC_CMOS_D4 = 142, /*!< Data Bit 4 */ - FUNC_CMOS_D5 = 143, /*!< Data Bit 5 */ - FUNC_CMOS_D6 = 144, /*!< Data Bit 6 */ - FUNC_CMOS_D7 = 145, /*!< Data Bit 7 */ - FUNC_SCCB_SCLK = 146, /*!< SCCB Serial Clock */ - FUNC_SCCB_SDA = 147, /*!< SCCB Serial Data */ - FUNC_UART1_CTS = 148, /*!< UART1 Clear To Send */ - FUNC_UART1_DSR = 149, /*!< UART1 Data Set Ready */ - FUNC_UART1_DCD = 150, /*!< UART1 Data Carrier Detect */ - FUNC_UART1_RI = 151, /*!< UART1 Ring Indicator */ - FUNC_UART1_SIR_IN = 152, /*!< UART1 Serial Infrared Input */ - FUNC_UART1_DTR = 153, /*!< UART1 Data Terminal Ready */ - FUNC_UART1_RTS = 154, /*!< UART1 Request To Send */ - FUNC_UART1_OUT2 = 155, /*!< UART1 User-designated Output 2 */ - FUNC_UART1_OUT1 = 156, /*!< UART1 User-designated Output 1 */ - FUNC_UART1_SIR_OUT = 157, /*!< UART1 Serial Infrared Output */ - FUNC_UART1_BAUD = 158, /*!< UART1 Transmit Clock Output */ - FUNC_UART1_RE = 159, /*!< UART1 Receiver Output Enable */ - FUNC_UART1_DE = 160, /*!< UART1 Driver Output Enable */ - FUNC_UART1_RS485_EN = 161, /*!< UART1 RS485 Enable */ - FUNC_UART2_CTS = 162, /*!< UART2 Clear To Send */ - FUNC_UART2_DSR = 163, /*!< UART2 Data Set Ready */ - FUNC_UART2_DCD = 164, /*!< UART2 Data Carrier Detect */ - FUNC_UART2_RI = 165, /*!< UART2 Ring Indicator */ - FUNC_UART2_SIR_IN = 166, /*!< UART2 Serial Infrared Input */ - FUNC_UART2_DTR = 167, /*!< UART2 Data Terminal Ready */ - FUNC_UART2_RTS = 168, /*!< UART2 Request To Send */ - FUNC_UART2_OUT2 = 169, /*!< UART2 User-designated Output 2 */ - FUNC_UART2_OUT1 = 170, /*!< UART2 User-designated Output 1 */ - FUNC_UART2_SIR_OUT = 171, /*!< UART2 Serial Infrared Output */ - FUNC_UART2_BAUD = 172, /*!< UART2 Transmit Clock Output */ - FUNC_UART2_RE = 173, /*!< UART2 Receiver Output Enable */ - FUNC_UART2_DE = 174, /*!< UART2 Driver Output Enable */ - FUNC_UART2_RS485_EN = 175, /*!< UART2 RS485 Enable */ - FUNC_UART3_CTS = 176, /*!< UART3 Clear To Send */ - FUNC_UART3_DSR = 177, /*!< UART3 Data Set Ready */ - FUNC_UART3_DCD = 178, /*!< UART3 Data Carrier Detect */ - FUNC_UART3_RI = 179, /*!< UART3 Ring Indicator */ - FUNC_UART3_SIR_IN = 180, /*!< UART3 Serial Infrared Input */ - FUNC_UART3_DTR = 181, /*!< UART3 Data Terminal Ready */ - FUNC_UART3_RTS = 182, /*!< UART3 Request To Send */ - FUNC_UART3_OUT2 = 183, /*!< UART3 User-designated Output 2 */ - FUNC_UART3_OUT1 = 184, /*!< UART3 User-designated Output 1 */ - FUNC_UART3_SIR_OUT = 185, /*!< UART3 Serial Infrared Output */ - FUNC_UART3_BAUD = 186, /*!< UART3 Transmit Clock Output */ - FUNC_UART3_RE = 187, /*!< UART3 Receiver Output Enable */ - FUNC_UART3_DE = 188, /*!< UART3 Driver Output Enable */ - FUNC_UART3_RS485_EN = 189, /*!< UART3 RS485 Enable */ - FUNC_TIMER0_TOGGLE1 = 190, /*!< TIMER0 Toggle Output 1 */ - FUNC_TIMER0_TOGGLE2 = 191, /*!< TIMER0 Toggle Output 2 */ - FUNC_TIMER0_TOGGLE3 = 192, /*!< TIMER0 Toggle Output 3 */ - FUNC_TIMER0_TOGGLE4 = 193, /*!< TIMER0 Toggle Output 4 */ - FUNC_TIMER1_TOGGLE1 = 194, /*!< TIMER1 Toggle Output 1 */ - FUNC_TIMER1_TOGGLE2 = 195, /*!< TIMER1 Toggle Output 2 */ - FUNC_TIMER1_TOGGLE3 = 196, /*!< TIMER1 Toggle Output 3 */ - FUNC_TIMER1_TOGGLE4 = 197, /*!< TIMER1 Toggle Output 4 */ - FUNC_TIMER2_TOGGLE1 = 198, /*!< TIMER2 Toggle Output 1 */ - FUNC_TIMER2_TOGGLE2 = 199, /*!< TIMER2 Toggle Output 2 */ - FUNC_TIMER2_TOGGLE3 = 200, /*!< TIMER2 Toggle Output 3 */ - FUNC_TIMER2_TOGGLE4 = 201, /*!< TIMER2 Toggle Output 4 */ - FUNC_CLK_SPI2 = 202, /*!< Clock SPI2 */ - FUNC_CLK_I2C2 = 203, /*!< Clock I2C2 */ - FUNC_INTERNAL0 = 204, /*!< Internal function signal 0 */ - FUNC_INTERNAL1 = 205, /*!< Internal function signal 1 */ - FUNC_INTERNAL2 = 206, /*!< Internal function signal 2 */ - FUNC_INTERNAL3 = 207, /*!< Internal function signal 3 */ - FUNC_INTERNAL4 = 208, /*!< Internal function signal 4 */ - FUNC_INTERNAL5 = 209, /*!< Internal function signal 5 */ - FUNC_INTERNAL6 = 210, /*!< Internal function signal 6 */ - FUNC_INTERNAL7 = 211, /*!< Internal function signal 7 */ - FUNC_INTERNAL8 = 212, /*!< Internal function signal 8 */ - FUNC_INTERNAL9 = 213, /*!< Internal function signal 9 */ - FUNC_INTERNAL10 = 214, /*!< Internal function signal 10 */ - FUNC_INTERNAL11 = 215, /*!< Internal function signal 11 */ - FUNC_INTERNAL12 = 216, /*!< Internal function signal 12 */ - FUNC_INTERNAL13 = 217, /*!< Internal function signal 13 */ - FUNC_INTERNAL14 = 218, /*!< Internal function signal 14 */ - FUNC_INTERNAL15 = 219, /*!< Internal function signal 15 */ - FUNC_INTERNAL16 = 220, /*!< Internal function signal 16 */ - FUNC_INTERNAL17 = 221, /*!< Internal function signal 17 */ - FUNC_CONSTANT = 222, /*!< Constant function */ - FUNC_INTERNAL18 = 223, /*!< Internal function signal 18 */ - FUNC_DEBUG0 = 224, /*!< Debug function 0 */ - FUNC_DEBUG1 = 225, /*!< Debug function 1 */ - FUNC_DEBUG2 = 226, /*!< Debug function 2 */ - FUNC_DEBUG3 = 227, /*!< Debug function 3 */ - FUNC_DEBUG4 = 228, /*!< Debug function 4 */ - FUNC_DEBUG5 = 229, /*!< Debug function 5 */ - FUNC_DEBUG6 = 230, /*!< Debug function 6 */ - FUNC_DEBUG7 = 231, /*!< Debug function 7 */ - FUNC_DEBUG8 = 232, /*!< Debug function 8 */ - FUNC_DEBUG9 = 233, /*!< Debug function 9 */ - FUNC_DEBUG10 = 234, /*!< Debug function 10 */ - FUNC_DEBUG11 = 235, /*!< Debug function 11 */ - FUNC_DEBUG12 = 236, /*!< Debug function 12 */ - FUNC_DEBUG13 = 237, /*!< Debug function 13 */ - FUNC_DEBUG14 = 238, /*!< Debug function 14 */ - FUNC_DEBUG15 = 239, /*!< Debug function 15 */ - FUNC_DEBUG16 = 240, /*!< Debug function 16 */ - FUNC_DEBUG17 = 241, /*!< Debug function 17 */ - FUNC_DEBUG18 = 242, /*!< Debug function 18 */ - FUNC_DEBUG19 = 243, /*!< Debug function 19 */ - FUNC_DEBUG20 = 244, /*!< Debug function 20 */ - FUNC_DEBUG21 = 245, /*!< Debug function 21 */ - FUNC_DEBUG22 = 246, /*!< Debug function 22 */ - FUNC_DEBUG23 = 247, /*!< Debug function 23 */ - FUNC_DEBUG24 = 248, /*!< Debug function 24 */ - FUNC_DEBUG25 = 249, /*!< Debug function 25 */ - FUNC_DEBUG26 = 250, /*!< Debug function 26 */ - FUNC_DEBUG27 = 251, /*!< Debug function 27 */ - FUNC_DEBUG28 = 252, /*!< Debug function 28 */ - FUNC_DEBUG29 = 253, /*!< Debug function 29 */ - FUNC_DEBUG30 = 254, /*!< Debug function 30 */ - FUNC_DEBUG31 = 255, /*!< Debug function 31 */ - FUNC_MAX = 256, /*!< Function numbers */ -} fpioa_function_t; -/* clang-format on */ - -/** - * @brief FPIOA pull settings - * - * @note FPIOA pull settings description - * - * | PU | PD | Description | - * |-----|-----|-----------------------------------| - * | 0 | 0 | No Pull | - * | 0 | 1 | Pull Down | - * | 1 | 0 | Pull Up | - * | 1 | 1 | Undefined | - * - */ - -/* clang-format off */ -typedef enum _fpioa_pull -{ - FPIOA_PULL_NONE, /*!< No Pull */ - FPIOA_PULL_DOWN, /*!< Pull Down */ - FPIOA_PULL_UP, /*!< Pull Up */ - FPIOA_PULL_MAX /*!< Count of pull settings */ -} fpioa_pull_t; -/* clang-format on */ - -/** - * @brief FPIOA driving settings - * - * @note FPIOA driving settings description - * There are 16 kinds of driving settings - * - * @note Low Level Output Current - * - * |DS[3:0] |Min(mA)|Typ(mA)|Max(mA)| - * |--------|-------|-------|-------| - * |0000 |3.2 |5.4 |8.3 | - * |0001 |4.7 |8.0 |12.3 | - * |0010 |6.3 |10.7 |16.4 | - * |0011 |7.8 |13.2 |20.2 | - * |0100 |9.4 |15.9 |24.2 | - * |0101 |10.9 |18.4 |28.1 | - * |0110 |12.4 |20.9 |31.8 | - * |0111 |13.9 |23.4 |35.5 | - * - * @note High Level Output Current - * - * |DS[3:0] |Min(mA)|Typ(mA)|Max(mA)| - * |--------|-------|-------|-------| - * |0000 |5.0 |7.6 |11.2 | - * |0001 |7.5 |11.4 |16.8 | - * |0010 |10.0 |15.2 |22.3 | - * |0011 |12.4 |18.9 |27.8 | - * |0100 |14.9 |22.6 |33.3 | - * |0101 |17.4 |26.3 |38.7 | - * |0110 |19.8 |30.0 |44.1 | - * |0111 |22.3 |33.7 |49.5 | - * - */ - -/* clang-format off */ -typedef enum _fpioa_driving -{ - FPIOA_DRIVING_0, /*!< 0000 */ - FPIOA_DRIVING_1, /*!< 0001 */ - FPIOA_DRIVING_2, /*!< 0010 */ - FPIOA_DRIVING_3, /*!< 0011 */ - FPIOA_DRIVING_4, /*!< 0100 */ - FPIOA_DRIVING_5, /*!< 0101 */ - FPIOA_DRIVING_6, /*!< 0110 */ - FPIOA_DRIVING_7, /*!< 0111 */ - FPIOA_DRIVING_8, /*!< 1000 */ - FPIOA_DRIVING_9, /*!< 1001 */ - FPIOA_DRIVING_10, /*!< 1010 */ - FPIOA_DRIVING_11, /*!< 1011 */ - FPIOA_DRIVING_12, /*!< 1100 */ - FPIOA_DRIVING_13, /*!< 1101 */ - FPIOA_DRIVING_14, /*!< 1110 */ - FPIOA_DRIVING_15, /*!< 1111 */ - FPIOA_DRIVING_MAX /*!< Count of driving settings */ -} fpioa_driving_t; -/* clang-format on */ - -/** - * @brief FPIOA IO - * - * FPIOA IO is the specific pin of the chip package. Every IO - * has a 32bit width register that can independently implement - * schmitt trigger, invert input, invert output, strong pull - * up, driving selector, static input and static output. And more, - * it can implement any pin of any peripheral devices. - * - * @note FPIOA IO's register bits Layout - * - * | Bits | Name |Description | - * |-----------|----------|---------------------------------------------------| - * | 31 | PAD_DI | Read current IO's data input. | - * | 30:24 | NA | Reserved bits. | - * | 23 | ST | Schmitt trigger. | - * | 22 | DI_INV | Invert Data input. | - * | 21 | IE_INV | Invert the input enable signal. | - * | 20 | IE_EN | Input enable. It can disable or enable IO input. | - * | 19 | SL | Slew rate control enable. | - * | 18 | SPU | Strong pull up. | - * | 17 | PD | Pull select: 0 for pull down, 1 for pull up. | - * | 16 | PU | Pull enable. | - * | 15 | DO_INV | Invert the result of data output select (DO_SEL). | - * | 14 | DO_SEL | Data output select: 0 for DO, 1 for OE. | - * | 13 | OE_INV | Invert the output enable signal. | - * | 12 | OE_EN | Output enable.It can disable or enable IO output. | - * | 11:8 | DS | Driving selector. | - * | 7:0 | CH_SEL | Channel select from 256 input. | - * - */ -typedef struct _fpioa_io_config -{ - uint32_t ch_sel : 8; - /*!< Channel select from 256 input. */ - uint32_t ds : 4; - /*!< Driving selector. */ - uint32_t oe_en : 1; - /*!< Static output enable, will AND with OE_INV. */ - uint32_t oe_inv : 1; - /*!< Invert output enable. */ - uint32_t do_sel : 1; - /*!< Data output select: 0 for DO, 1 for OE. */ - uint32_t do_inv : 1; - /*!< Invert the result of data output select (DO_SEL). */ - uint32_t pu : 1; - /*!< Pull up enable. 0 for nothing, 1 for pull up. */ - uint32_t pd : 1; - /*!< Pull down enable. 0 for nothing, 1 for pull down. */ - uint32_t resv0 : 1; - /*!< Reserved bits. */ - uint32_t sl : 1; - /*!< Slew rate control enable. */ - uint32_t ie_en : 1; - /*!< Static input enable, will AND with IE_INV. */ - uint32_t ie_inv : 1; - /*!< Invert input enable. */ - uint32_t di_inv : 1; - /*!< Invert Data input. */ - uint32_t st : 1; - /*!< Schmitt trigger. */ - uint32_t resv1 : 7; - /*!< Reserved bits. */ - uint32_t pad_di : 1; - /*!< Read current IO's data input. */ -} __attribute__((packed, aligned(4))) fpioa_io_config_t; - -/** - * @brief FPIOA tie setting - * - * FPIOA Object have 48 IO pin object and 256 bit input tie bits. - * All SPI arbitration signal will tie high by default. - * - * @note FPIOA function tie bits RAM Layout - * - * | Address | Name |Description | - * |-----------|------------------|----------------------------------| - * | 0x000 | TIE_EN[31:0] | Input tie enable bits [31:0] | - * | 0x004 | TIE_EN[63:32] | Input tie enable bits [63:32] | - * | 0x008 | TIE_EN[95:64] | Input tie enable bits [95:64] | - * | 0x00C | TIE_EN[127:96] | Input tie enable bits [127:96] | - * | 0x010 | TIE_EN[159:128] | Input tie enable bits [159:128] | - * | 0x014 | TIE_EN[191:160] | Input tie enable bits [191:160] | - * | 0x018 | TIE_EN[223:192] | Input tie enable bits [223:192] | - * | 0x01C | TIE_EN[255:224] | Input tie enable bits [255:224] | - * | 0x020 | TIE_VAL[31:0] | Input tie value bits [31:0] | - * | 0x024 | TIE_VAL[63:32] | Input tie value bits [63:32] | - * | 0x028 | TIE_VAL[95:64] | Input tie value bits [95:64] | - * | 0x02C | TIE_VAL[127:96] | Input tie value bits [127:96] | - * | 0x030 | TIE_VAL[159:128] | Input tie value bits [159:128] | - * | 0x034 | TIE_VAL[191:160] | Input tie value bits [191:160] | - * | 0x038 | TIE_VAL[223:192] | Input tie value bits [223:192] | - * | 0x03C | TIE_VAL[255:224] | Input tie value bits [255:224] | - * - * @note Function which input tie high by default - * - * | Name |Description | - * |---------------|---------------------------------------| - * | SPI0_ARB | Arbitration function of SPI master 0 | - * | SPI1_ARB | Arbitration function of SPI master 1 | - * - * Tie high means the SPI Arbitration input is 1 - * - */ -typedef struct _fpioa_tie -{ - uint32_t en[FUNC_MAX / 32]; - /*!< FPIOA GPIO multiplexer tie enable array */ - uint32_t val[FUNC_MAX / 32]; - /*!< FPIOA GPIO multiplexer tie value array */ -} __attribute__((packed, aligned(4))) fpioa_tie_t; - -/** - * @brief FPIOA Object - * - * FPIOA Object have 48 IO pin object and 256 bit input tie bits. - * All SPI arbitration signal will tie high by default. - * - * @note FPIOA IO Pin RAM Layout - * - * | Address | Name |Description | - * |-----------|----------|--------------------------------| - * | 0x000 | PAD0 | FPIOA GPIO multiplexer io 0 | - * | 0x004 | PAD1 | FPIOA GPIO multiplexer io 1 | - * | 0x008 | PAD2 | FPIOA GPIO multiplexer io 2 | - * | 0x00C | PAD3 | FPIOA GPIO multiplexer io 3 | - * | 0x010 | PAD4 | FPIOA GPIO multiplexer io 4 | - * | 0x014 | PAD5 | FPIOA GPIO multiplexer io 5 | - * | 0x018 | PAD6 | FPIOA GPIO multiplexer io 6 | - * | 0x01C | PAD7 | FPIOA GPIO multiplexer io 7 | - * | 0x020 | PAD8 | FPIOA GPIO multiplexer io 8 | - * | 0x024 | PAD9 | FPIOA GPIO multiplexer io 9 | - * | 0x028 | PAD10 | FPIOA GPIO multiplexer io 10 | - * | 0x02C | PAD11 | FPIOA GPIO multiplexer io 11 | - * | 0x030 | PAD12 | FPIOA GPIO multiplexer io 12 | - * | 0x034 | PAD13 | FPIOA GPIO multiplexer io 13 | - * | 0x038 | PAD14 | FPIOA GPIO multiplexer io 14 | - * | 0x03C | PAD15 | FPIOA GPIO multiplexer io 15 | - * | 0x040 | PAD16 | FPIOA GPIO multiplexer io 16 | - * | 0x044 | PAD17 | FPIOA GPIO multiplexer io 17 | - * | 0x048 | PAD18 | FPIOA GPIO multiplexer io 18 | - * | 0x04C | PAD19 | FPIOA GPIO multiplexer io 19 | - * | 0x050 | PAD20 | FPIOA GPIO multiplexer io 20 | - * | 0x054 | PAD21 | FPIOA GPIO multiplexer io 21 | - * | 0x058 | PAD22 | FPIOA GPIO multiplexer io 22 | - * | 0x05C | PAD23 | FPIOA GPIO multiplexer io 23 | - * | 0x060 | PAD24 | FPIOA GPIO multiplexer io 24 | - * | 0x064 | PAD25 | FPIOA GPIO multiplexer io 25 | - * | 0x068 | PAD26 | FPIOA GPIO multiplexer io 26 | - * | 0x06C | PAD27 | FPIOA GPIO multiplexer io 27 | - * | 0x070 | PAD28 | FPIOA GPIO multiplexer io 28 | - * | 0x074 | PAD29 | FPIOA GPIO multiplexer io 29 | - * | 0x078 | PAD30 | FPIOA GPIO multiplexer io 30 | - * | 0x07C | PAD31 | FPIOA GPIO multiplexer io 31 | - * | 0x080 | PAD32 | FPIOA GPIO multiplexer io 32 | - * | 0x084 | PAD33 | FPIOA GPIO multiplexer io 33 | - * | 0x088 | PAD34 | FPIOA GPIO multiplexer io 34 | - * | 0x08C | PAD35 | FPIOA GPIO multiplexer io 35 | - * | 0x090 | PAD36 | FPIOA GPIO multiplexer io 36 | - * | 0x094 | PAD37 | FPIOA GPIO multiplexer io 37 | - * | 0x098 | PAD38 | FPIOA GPIO multiplexer io 38 | - * | 0x09C | PAD39 | FPIOA GPIO multiplexer io 39 | - * | 0x0A0 | PAD40 | FPIOA GPIO multiplexer io 40 | - * | 0x0A4 | PAD41 | FPIOA GPIO multiplexer io 41 | - * | 0x0A8 | PAD42 | FPIOA GPIO multiplexer io 42 | - * | 0x0AC | PAD43 | FPIOA GPIO multiplexer io 43 | - * | 0x0B0 | PAD44 | FPIOA GPIO multiplexer io 44 | - * | 0x0B4 | PAD45 | FPIOA GPIO multiplexer io 45 | - * | 0x0B8 | PAD46 | FPIOA GPIO multiplexer io 46 | - * | 0x0BC | PAD47 | FPIOA GPIO multiplexer io 47 | - * - */ -typedef struct _fpioa -{ - fpioa_io_config_t io[FPIOA_NUM_IO]; - /*!< FPIOA GPIO multiplexer io array */ - fpioa_tie_t tie; - /*!< FPIOA GPIO multiplexer tie */ -} __attribute__((packed, aligned(4))) fpioa_t; - -/** - * @brief FPIOA object instanse - */ -extern volatile fpioa_t *const fpioa; - -/** - * @brief Initialize FPIOA user custom default settings - * - * @note This function will set all FPIOA pad registers to user-defined - * values from kconfig - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_init(void); - -/** - * @brief Get IO configuration - * - * @param[in] number The IO number - * @param cfg Pointer to struct of IO configuration for specified IO - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_get_io(int number, fpioa_io_config_t *cfg); - -/** - * @brief Set IO configuration - * - * @param[in] number The IO number - * @param[in] cfg Pointer to struct of IO configuration for specified IO - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_io(int number, fpioa_io_config_t *cfg); - -/** - * @brief Set IO configuration with function number - * - * @note The default IO configuration which bind to function number will - * set automatically - * - * @param[in] number The IO number - * @param[in] function The function enum number - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_function_raw(int number, fpioa_function_t function); - -/** - * @brief Set only IO configuration with function number - * - * @note The default IO configuration which bind to function number will - * set automatically - * - * @param[in] number The IO number - * @param[in] function The function enum number - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_function(int number, fpioa_function_t function); - -/** - * @brief Set tie enable to function - * - * @param[in] function The function enum number - * @param[in] enable Tie enable to set, 1 is enable, 0 is disable - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_tie_enable(fpioa_function_t function, int enable); - -/** - * @brief Set tie value to function - * - * @param[in] function The function enum number - * @param[in] value Tie value to set, 1 is HIGH, 0 is LOW - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_tie_value(fpioa_function_t function, int value); - -/** - * @brief Set IO pull function - * - * @param[in] number The IO number - * @param[in] pull The pull enum number - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_io_pull(int number, fpioa_pull_t pull); - -/** - * @brief Get IO pull function - * - * @param[in] number The IO number - * - * @return result - * - -1 Fail - * - Other The pull enum number - */ -int fpioa_get_io_pull(int number); - -/** - * @brief Set IO driving - * - * @param[in] number The IO number - * @param[in] driving The driving enum number - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_io_driving(int number, fpioa_driving_t driving); - -/** - * @brief Get IO driving - * - * @param[in] number The IO number - * - * @return result - * - -1 Fail - * - Other The driving enum number - */ -int fpioa_get_io_driving(int number); - -/** - * @brief Get IO by function - * - * @param[in] function The function enum number - * - * @return result - * - -1 Fail - * - Other The IO number - */ -int fpioa_get_io_by_function(fpioa_function_t function); - -/** - * @brief Set IO slew rate control - * - * @param[in] number The IO number - * @param[in] sl_value Enable slew rate. 0: disable 1:enable - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_sl(int number, uint8_t sl_enable); - -/** - * @brief Set IO schmitt trigger - * - * @param[in] number The IO number - * @param[in] st_enable Enable schmitt trigger. 0: disable 1:enable - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_st(int number, uint8_t st_enable); - -/** - * @brief Set IO output invert enable - * - * @param[in] number The IO number - * @param[in] inv_enable Enable output invert. 0: disable 1:enable - * - * @return result - * - 0 Success - * - Other Fail - */ -int fpioa_set_oe_inv(int number, uint8_t inv_enable); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_FPIOA_H */ diff --git a/Kboot/src/bootloader_hi/include/gpiohs.h b/Kboot/src/bootloader_hi/include/gpiohs.h deleted file mode 100644 index f4bad1c..0000000 --- a/Kboot/src/bootloader_hi/include/gpiohs.h +++ /dev/null @@ -1,256 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_GPIOHS_H -#define _DRIVER_GPIOHS_H - -#include -#include -#include "platform.h" -//#include "plic.h" -#ifdef __cplusplus -extern "C" { -#endif - -/* clang-format off */ -/* Register address offsets */ -#define GPIOHS_INPUT_VAL (0x00) -#define GPIOHS_INPUT_EN (0x04) -#define GPIOHS_OUTPUT_EN (0x08) -#define GPIOHS_OUTPUT_VAL (0x0C) -#define GPIOHS_PULLUP_EN (0x10) -#define GPIOHS_DRIVE (0x14) -#define GPIOHS_RISE_IE (0x18) -#define GPIOHS_RISE_IP (0x1C) -#define GPIOHS_FALL_IE (0x20) -#define GPIOHS_FALL_IP (0x24) -#define GPIOHS_HIGH_IE (0x28) -#define GPIOHS_HIGH_IP (0x2C) -#define GPIOHS_LOW_IE (0x30) -#define GPIOHS_LOW_IP (0x34) -#define GPIOHS_IOF_EN (0x38) -#define GPIOHS_IOF_SEL (0x3C) -#define GPIOHS_OUTPUT_XOR (0x40) -/* clang-format on */ - -typedef enum _gpio_drive_mode -{ - GPIO_DM_INPUT, - GPIO_DM_INPUT_PULL_DOWN, - GPIO_DM_INPUT_PULL_UP, - GPIO_DM_OUTPUT, -} gpio_drive_mode_t; - -typedef enum _gpio_pin_edge -{ - GPIO_PE_NONE, - GPIO_PE_FALLING, - GPIO_PE_RISING, - GPIO_PE_BOTH, - GPIO_PE_LOW, - GPIO_PE_HIGH = 8, -} gpio_pin_edge_t; - -typedef enum _gpio_pin_value -{ - GPIO_PV_LOW, - GPIO_PV_HIGH -} gpio_pin_value_t; - -/** - * @brief GPIO bits raw object - */ -typedef struct _gpiohs_raw -{ - /* Address offset 0x00 */ - uint32_t input_val; - /* Address offset 0x04 */ - uint32_t input_en; - /* Address offset 0x08 */ - uint32_t output_en; - /* Address offset 0x0c */ - uint32_t output_val; - /* Address offset 0x10 */ - uint32_t pullup_en; - /* Address offset 0x14 */ - uint32_t drive; - /* Address offset 0x18 */ - uint32_t rise_ie; - /* Address offset 0x1c */ - uint32_t rise_ip; - /* Address offset 0x20 */ - uint32_t fall_ie; - /* Address offset 0x24 */ - uint32_t fall_ip; - /* Address offset 0x28 */ - uint32_t high_ie; - /* Address offset 0x2c */ - uint32_t high_ip; - /* Address offset 0x30 */ - uint32_t low_ie; - /* Address offset 0x34 */ - uint32_t low_ip; - /* Address offset 0x38 */ - uint32_t iof_en; - /* Address offset 0x3c */ - uint32_t iof_sel; - /* Address offset 0x40 */ - uint32_t output_xor; -} __attribute__((packed, aligned(4))) gpiohs_raw_t; - -/** - * @brief GPIO bits object - */ -typedef struct _gpiohs_bits -{ - uint32_t b0 : 1; - uint32_t b1 : 1; - uint32_t b2 : 1; - uint32_t b3 : 1; - uint32_t b4 : 1; - uint32_t b5 : 1; - uint32_t b6 : 1; - uint32_t b7 : 1; - uint32_t b8 : 1; - uint32_t b9 : 1; - uint32_t b10 : 1; - uint32_t b11 : 1; - uint32_t b12 : 1; - uint32_t b13 : 1; - uint32_t b14 : 1; - uint32_t b15 : 1; - uint32_t b16 : 1; - uint32_t b17 : 1; - uint32_t b18 : 1; - uint32_t b19 : 1; - uint32_t b20 : 1; - uint32_t b21 : 1; - uint32_t b22 : 1; - uint32_t b23 : 1; - uint32_t b24 : 1; - uint32_t b25 : 1; - uint32_t b26 : 1; - uint32_t b27 : 1; - uint32_t b28 : 1; - uint32_t b29 : 1; - uint32_t b30 : 1; - uint32_t b31 : 1; -} __attribute__((packed, aligned(4))) gpiohs_bits_t; - -/** - * @brief GPIO bits multi access union - */ -typedef union _gpiohs_u32 -{ - /* 32x1 bit mode */ - uint32_t u32[1]; - /* 16x2 bit mode */ - uint16_t u16[2]; - /* 8x4 bit mode */ - uint8_t u8[4]; - /* 1 bit mode */ - gpiohs_bits_t bits; -} __attribute__((packed, aligned(4))) gpiohs_u32_t; - -/** - * @brief GPIO object - * - * The GPIO controller is a peripheral device mapped in the - * internal memory map, discoverable in the Configuration String. - * It is responsible for low-level configuration of the actual - * GPIO pads on the device (direction, pull up-enable, and drive - * value), as well as selecting between various sources of the - * controls for these signals. The GPIO controller allows seperate - * configuration of each of N GPIO bits. - * - * Once the interrupt is pending, it will remain set until a 1 is - * written to the *_ip register at that bit. - */ - -typedef struct _gpiohs -{ - /* Address offset 0x00, Input Values */ - gpiohs_u32_t input_val; - /* Address offset 0x04, Input enable */ - gpiohs_u32_t input_en; - /* Address offset 0x08, Output enable */ - gpiohs_u32_t output_en; - /* Address offset 0x0c, Onput Values */ - gpiohs_u32_t output_val; - /* Address offset 0x10, Internal Pull-Ups enable */ - gpiohs_u32_t pullup_en; - /* Address offset 0x14, Drive Strength */ - gpiohs_u32_t drive; - /* Address offset 0x18, Rise interrupt enable */ - gpiohs_u32_t rise_ie; - /* Address offset 0x1c, Rise interrupt pending */ - gpiohs_u32_t rise_ip; - /* Address offset 0x20, Fall interrupt enable */ - gpiohs_u32_t fall_ie; - /* Address offset 0x24, Fall interrupt pending */ - gpiohs_u32_t fall_ip; - /* Address offset 0x28, High interrupt enable */ - gpiohs_u32_t high_ie; - /* Address offset 0x2c, High interrupt pending */ - gpiohs_u32_t high_ip; - /* Address offset 0x30, Low interrupt enable */ - gpiohs_u32_t low_ie; - /* Address offset 0x34, Low interrupt pending */ - gpiohs_u32_t low_ip; - /* Address offset 0x38, HW I/O Function enable */ - gpiohs_u32_t iof_en; - /* Address offset 0x3c, HW I/O Function select */ - gpiohs_u32_t iof_sel; - /* Address offset 0x40, Output XOR (invert) */ - gpiohs_u32_t output_xor; -} __attribute__((packed, aligned(4))) gpiohs_t; - -/** - * @brief GPIO High-speed object instanse - */ -extern volatile gpiohs_t *const gpiohs; - -/** - * @brief Set Gpiohs drive mode - * - * @param[in] pin Gpiohs pin - * @param[in] mode Gpiohs pin drive mode - */ -void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode); - -/** - * @brief Get Gpiohs pin value - * - * @param[in] pin Gpiohs pin - * @return Pin value - * - * - GPIO_PV_Low Gpiohs pin low - * - GPIO_PV_High Gpiohs pin high - */ -gpio_pin_value_t gpiohs_get_pin(uint8_t pin); - -/** - * @brief Set Gpiohs pin value - * - * @param[in] pin Gpiohs pin - * @param[in] value Gpiohs pin value - */ -void gpiohs_set_pin(uint8_t pin, gpio_pin_value_t value); - - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_GPIOHS_H */ diff --git a/Kboot/src/bootloader_hi/include/platform.h b/Kboot/src/bootloader_hi/include/platform.h deleted file mode 100644 index a2800a9..0000000 --- a/Kboot/src/bootloader_hi/include/platform.h +++ /dev/null @@ -1,98 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _BSP_PLATFORM_H -#define _BSP_PLATFORM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* clang-format off */ -/* Register base address */ - -/* Under Coreplex */ -#define CLINT_BASE_ADDR (0x02000000U) -#define PLIC_BASE_ADDR (0x0C000000U) - -/* Under TileLink */ -#define UARTHS_BASE_ADDR (0x38000000U) -#define GPIOHS_BASE_ADDR (0x38001000U) - -/* Under AXI 64 bit */ -#define RAM_BASE_ADDR (0x80000000U) -#define RAM_SIZE (6 * 1024 * 1024U) - -#define IO_BASE_ADDR (0x40000000U) -#define IO_SIZE (6 * 1024 * 1024U) - -#define AI_RAM_BASE_ADDR (0x80600000U) -#define AI_RAM_SIZE (2 * 1024 * 1024U) - -#define AI_IO_BASE_ADDR (0x40600000U) -#define AI_IO_SIZE (2 * 1024 * 1024U) - -#define AI_BASE_ADDR (0x40800000U) -#define AI_SIZE (12 * 1024 * 1024U) - -#define FFT_BASE_ADDR (0x42000000U) -#define FFT_SIZE (4 * 1024 * 1024U) - -#define ROM_BASE_ADDR (0x88000000U) -#define ROM_SIZE (128 * 1024U) - -/* Under AHB 32 bit */ -#define DMAC_BASE_ADDR (0x50000000U) - -/* Under APB1 32 bit */ -#define GPIO_BASE_ADDR (0x50200000U) -#define UART1_BASE_ADDR (0x50210000U) -#define UART2_BASE_ADDR (0x50220000U) -#define UART3_BASE_ADDR (0x50230000U) -#define SPI_SLAVE_BASE_ADDR (0x50240000U) -#define I2S0_BASE_ADDR (0x50250000U) -#define I2S1_BASE_ADDR (0x50260000U) -#define I2S2_BASE_ADDR (0x50270000U) -#define I2C0_BASE_ADDR (0x50280000U) -#define I2C1_BASE_ADDR (0x50290000U) -#define I2C2_BASE_ADDR (0x502A0000U) -#define FPIOA_BASE_ADDR (0x502B0000U) -#define SHA256_BASE_ADDR (0x502C0000U) -#define TIMER0_BASE_ADDR (0x502D0000U) -#define TIMER1_BASE_ADDR (0x502E0000U) -#define TIMER2_BASE_ADDR (0x502F0000U) - -/* Under APB2 32 bit */ -#define WDT0_BASE_ADDR (0x50400000U) -#define WDT1_BASE_ADDR (0x50410000U) -#define OTP_BASE_ADDR (0x50420000U) -#define DVP_BASE_ADDR (0x50430000U) -#define SYSCTL_BASE_ADDR (0x50440000U) -#define AES_BASE_ADDR (0x50450000U) -#define RTC_BASE_ADDR (0x50460000U) - - -/* Under APB3 32 bit */ -#define SPI0_BASE_ADDR (0x52000000U) -#define SPI1_BASE_ADDR (0x53000000U) -#define SPI3_BASE_ADDR (0x54000000U) - -/* clang-format on */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_PLATFORM_H */ diff --git a/Kboot/src/bootloader_hi/include/sha256.h b/Kboot/src/bootloader_hi/include/sha256.h deleted file mode 100644 index 4210e54..0000000 --- a/Kboot/src/bootloader_hi/include/sha256.h +++ /dev/null @@ -1,130 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _SHA256_H -#define _SHA256_H -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define ENABLE_SHA (0x1) -#define SHA256_BIG_ENDIAN (0x1) - -#define SHA256_HASH_LEN 32 -#define SHA256_HASH_WORDS 8 -#define SHA256_BLOCK_LEN 64L - -typedef struct _sha_num_reg -{ - /* The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit. */ - uint32_t sha_data_cnt : 16; - /* currently calculated block number. 512bit=1block*/ - uint32_t sha_data_num : 16; -} __attribute__((packed, aligned(4))) sha_num_reg_t; - -typedef struct _sha_function_reg_0 -{ - /* write:SHA256 enable register. read:Calculation completed flag */ - uint32_t sha_en : 1; - uint32_t reserved00 : 7; - /* SHA256 calculation overflow flag */ - uint32_t sha_overflow : 1; - uint32_t reserved01 : 7; - /* Endian setting; b'0:little endian b'1:big endian */ - uint32_t sha_endian : 1; - uint32_t reserved02 : 15; -} __attribute__((packed, aligned(4))) sha_function_reg_0_t; - -typedef struct _sha_function_reg_1 -{ - /* Sha and DMA handshake signals enable.b'1:enable;b'0:disable */ - uint32_t dma_en : 1; - uint32_t reserved10 : 7; - /* b'1:sha256 fifo is full; b'0:not full */ - uint32_t fifo_in_full : 1; - uint32_t reserved11 : 23; -} __attribute__((packed, aligned(4))) sha_function_reg_1_t; - -typedef struct _sha256 -{ - /* Calculated sha256 return value. */ - uint32_t sha_result[8]; - /* SHA256 input data from this register. */ - uint32_t sha_data_in1; - uint32_t reselved0; - sha_num_reg_t sha_num_reg; - sha_function_reg_0_t sha_function_reg_0; - uint32_t reserved1; - sha_function_reg_1_t sha_function_reg_1; -} __attribute__((packed, aligned(4))) sha256_t; - -typedef struct _sha256_context -{ - size_t total_len; - size_t buffer_len; - union - { - uint32_t words[16]; - uint8_t bytes[64]; - } buffer; -} sha256_context_t; - -/** - * @brief Init SHA256 calculation context - * - * @param[in] context SHA256 context object - * - */ -void sha256_init(sha256_context_t *context, size_t input_len); - -/** - * @brief Called repeatedly with chunks of the message to be hashed - * - * @param[in] context SHA256 context object - * @param[in] data_buf data chunk to be hashed - * @param[in] buf_len length of data chunk - * - */ -void sha256_update(sha256_context_t *context, const void *input, size_t input_len); - -/** - * @brief Finish SHA256 hash process, output the result. - * - * @param[in] context SHA256 context object - * @param[out] output The buffer where SHA256 hash will be output - * - */ -void sha256_final(sha256_context_t *context, uint8_t *output); - -/** - * @brief Simple SHA256 hash once. - * - * @param[in] data Data will be hashed - * @param[in] data_len Data length - * @param[out] output Output buffer - * - */ -void sha256_hard_calculate(const uint8_t *input, size_t input_len, uint8_t *output); - - -int usleep(uint64_t usec); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/Kboot/src/bootloader_hi/include/spi.h b/Kboot/src/bootloader_hi/include/spi.h deleted file mode 100644 index 2646cf8..0000000 --- a/Kboot/src/bootloader_hi/include/spi.h +++ /dev/null @@ -1,123 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_SPI_H -#define _DRIVER_SPI_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* clang-format off */ -typedef struct _spi -{ - /* SPI Control Register 0 (0x00)*/ - volatile uint32_t ctrlr0; - /* SPI Control Register 1 (0x04)*/ - volatile uint32_t ctrlr1; - /* SPI Enable Register (0x08)*/ - volatile uint32_t ssienr; - /* SPI Microwire Control Register (0x0c)*/ - volatile uint32_t mwcr; - /* SPI Slave Enable Register (0x10)*/ - volatile uint32_t ser; - /* SPI Baud Rate Select (0x14)*/ - volatile uint32_t baudr; - /* SPI Transmit FIFO Threshold Level (0x18)*/ - volatile uint32_t txftlr; - /* SPI Receive FIFO Threshold Level (0x1c)*/ - volatile uint32_t rxftlr; - /* SPI Transmit FIFO Level Register (0x20)*/ - volatile uint32_t txflr; - /* SPI Receive FIFO Level Register (0x24)*/ - volatile uint32_t rxflr; - /* SPI Status Register (0x28)*/ - volatile uint32_t sr; - /* SPI Interrupt Mask Register (0x2c)*/ - volatile uint32_t imr; - /* SPI Interrupt Status Register (0x30)*/ - volatile uint32_t isr; - /* SPI Raw Interrupt Status Register (0x34)*/ - volatile uint32_t risr; - /* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38)*/ - volatile uint32_t txoicr; - /* SPI Receive FIFO Overflow Interrupt Clear Register (0x3c)*/ - volatile uint32_t rxoicr; - /* SPI Receive FIFO Underflow Interrupt Clear Register (0x40)*/ - volatile uint32_t rxuicr; - /* SPI Multi-Master Interrupt Clear Register (0x44)*/ - volatile uint32_t msticr; - /* SPI Interrupt Clear Register (0x48)*/ - volatile uint32_t icr; - /* SPI DMA Control Register (0x4c)*/ - volatile uint32_t dmacr; - /* SPI DMA Transmit Data Level (0x50)*/ - volatile uint32_t dmatdlr; - /* SPI DMA Receive Data Level (0x54)*/ - volatile uint32_t dmardlr; - /* SPI Identification Register (0x58)*/ - volatile uint32_t idr; - /* SPI DWC_ssi component version (0x5c)*/ - volatile uint32_t ssic_version_id; - /* SPI Data Register 0-36 (0x60 -- 0xec)*/ - volatile uint32_t dr[36]; - /* SPI RX Sample Delay Register (0xf0)*/ - volatile uint32_t rx_sample_delay; - /* SPI SPI Control Register (0xf4)*/ - volatile uint32_t spi_ctrlr0; - /* reserved (0xf8)*/ - volatile uint32_t resv; - /* SPI XIP Mode bits (0xfc)*/ - volatile uint32_t xip_mode_bits; - /* SPI XIP INCR transfer opcode (0x100)*/ - volatile uint32_t xip_incr_inst; - /* SPI XIP WRAP transfer opcode (0x104)*/ - volatile uint32_t xip_wrap_inst; - /* SPI XIP Control Register (0x108)*/ - volatile uint32_t xip_ctrl; - /* SPI XIP Slave Enable Register (0x10c)*/ - volatile uint32_t xip_ser; - /* SPI XIP Receive FIFO Overflow Interrupt Clear Register (0x110)*/ - volatile uint32_t xrxoicr; - /* SPI XIP time out register for continuous transfers (0x114)*/ - volatile uint32_t xip_cnt_time_out; - volatile uint32_t endian; -} __attribute__((packed, aligned(4))) spi_t; -/* clang-format on */ - -typedef enum _spi_work_mode -{ - SPI_WORK_MODE_0, - SPI_WORK_MODE_1, - SPI_WORK_MODE_2, - SPI_WORK_MODE_3, -} spi_work_mode_t; - -typedef enum _spi_frame_format -{ - SPI_FF_STANDARD, - SPI_FF_DUAL, - SPI_FF_QUAD, - SPI_FF_OCTAL -} spi_frame_format_t; - - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_SPI_H */ diff --git a/Kboot/src/bootloader_hi/include/sysctl.h b/Kboot/src/bootloader_hi/include/sysctl.h deleted file mode 100644 index b37bd64..0000000 --- a/Kboot/src/bootloader_hi/include/sysctl.h +++ /dev/null @@ -1,886 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_SYSCTL_H -#define _DRIVER_SYSCTL_H - -#include -#include "platform.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#define DEFAULT_CPU_CLOCK 390000000 - - -/** - * @brief System controller register - * - * @note System controller register table - * - * | Offset | Name | Description | - * |-----------|----------------|-------------------------------------| - * | 0x00 | git_id | Git short commit id | - * | 0x04 | clk_freq | System clock base frequency | - * | 0x08 | pll0 | PLL0 controller | - * | 0x0c | pll1 | PLL1 controller | - * | 0x10 | pll2 | PLL2 controller | - * | 0x14 | resv5 | Reserved | - * | 0x18 | pll_lock | PLL lock tester | - * | 0x1c | rom_error | AXI ROM detector | - * | 0x20 | clk_sel0 | Clock select controller0 | - * | 0x24 | clk_sel1 | Clock select controller1 | - * | 0x28 | clk_en_cent | Central clock enable | - * | 0x2c | clk_en_peri | Peripheral clock enable | - * | 0x30 | soft_reset | Soft reset ctrl | - * | 0x34 | peri_reset | Peripheral reset controller | - * | 0x38 | clk_th0 | Clock threshold controller 0 | - * | 0x3c | clk_th1 | Clock threshold controller 1 | - * | 0x40 | clk_th2 | Clock threshold controller 2 | - * | 0x44 | clk_th3 | Clock threshold controller 3 | - * | 0x48 | clk_th4 | Clock threshold controller 4 | - * | 0x4c | clk_th5 | Clock threshold controller 5 | - * | 0x50 | clk_th6 | Clock threshold controller 6 | - * | 0x54 | misc | Miscellaneous controller | - * | 0x58 | peri | Peripheral controller | - * | 0x5c | spi_sleep | SPI sleep controller | - * | 0x60 | reset_status | Reset source status | - * | 0x64 | dma_sel0 | DMA handshake selector | - * | 0x68 | dma_sel1 | DMA handshake selector | - * | 0x6c | power_sel | IO Power Mode Select controller | - * | 0x70 | resv28 | Reserved | - * | 0x74 | resv29 | Reserved | - * | 0x78 | resv30 | Reserved | - * | 0x7c | resv31 | Reserved | - * - */ - -typedef enum _sysctl_pll_t -{ - SYSCTL_PLL0, - SYSCTL_PLL1, - SYSCTL_PLL2, - SYSCTL_PLL_MAX -} sysctl_pll_t; - -typedef enum _sysctl_clock_source_t -{ - SYSCTL_SOURCE_IN0, - SYSCTL_SOURCE_PLL0, - SYSCTL_SOURCE_PLL1, - SYSCTL_SOURCE_PLL2, - SYSCTL_SOURCE_ACLK, - SYSCTL_SOURCE_MAX -} sysctl_clock_source_t; - -typedef enum _sysctl_dma_channel_t -{ - SYSCTL_DMA_CHANNEL_0, - SYSCTL_DMA_CHANNEL_1, - SYSCTL_DMA_CHANNEL_2, - SYSCTL_DMA_CHANNEL_3, - SYSCTL_DMA_CHANNEL_4, - SYSCTL_DMA_CHANNEL_5, - SYSCTL_DMA_CHANNEL_MAX -} sysctl_dma_channel_t; - -typedef enum _sysctl_dma_select_t -{ - SYSCTL_DMA_SELECT_SSI0_RX_REQ, - SYSCTL_DMA_SELECT_SSI0_TX_REQ, - SYSCTL_DMA_SELECT_SSI1_RX_REQ, - SYSCTL_DMA_SELECT_SSI1_TX_REQ, - SYSCTL_DMA_SELECT_SSI2_RX_REQ, - SYSCTL_DMA_SELECT_SSI2_TX_REQ, - SYSCTL_DMA_SELECT_SSI3_RX_REQ, - SYSCTL_DMA_SELECT_SSI3_TX_REQ, - SYSCTL_DMA_SELECT_I2C0_RX_REQ, - SYSCTL_DMA_SELECT_I2C0_TX_REQ, - SYSCTL_DMA_SELECT_I2C1_RX_REQ, - SYSCTL_DMA_SELECT_I2C1_TX_REQ, - SYSCTL_DMA_SELECT_I2C2_RX_REQ, - SYSCTL_DMA_SELECT_I2C2_TX_REQ, - SYSCTL_DMA_SELECT_UART1_RX_REQ, - SYSCTL_DMA_SELECT_UART1_TX_REQ, - SYSCTL_DMA_SELECT_UART2_RX_REQ, - SYSCTL_DMA_SELECT_UART2_TX_REQ, - SYSCTL_DMA_SELECT_UART3_RX_REQ, - SYSCTL_DMA_SELECT_UART3_TX_REQ, - SYSCTL_DMA_SELECT_AES_REQ, - SYSCTL_DMA_SELECT_SHA_RX_REQ, - SYSCTL_DMA_SELECT_AI_RX_REQ, - SYSCTL_DMA_SELECT_FFT_RX_REQ, - SYSCTL_DMA_SELECT_FFT_TX_REQ, - SYSCTL_DMA_SELECT_I2S0_TX_REQ, - SYSCTL_DMA_SELECT_I2S0_RX_REQ, - SYSCTL_DMA_SELECT_I2S1_TX_REQ, - SYSCTL_DMA_SELECT_I2S1_RX_REQ, - SYSCTL_DMA_SELECT_I2S2_TX_REQ, - SYSCTL_DMA_SELECT_I2S2_RX_REQ, - SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ, - SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ, - SYSCTL_DMA_SELECT_MAX -} sysctl_dma_select_t; - -/** - * @brief System controller clock id - */ -typedef enum _sysctl_clock_t -{ - SYSCTL_CLOCK_PLL0, - SYSCTL_CLOCK_PLL1, - SYSCTL_CLOCK_PLL2, - SYSCTL_CLOCK_CPU, - SYSCTL_CLOCK_SRAM0, - SYSCTL_CLOCK_SRAM1, - SYSCTL_CLOCK_APB0, - SYSCTL_CLOCK_APB1, - SYSCTL_CLOCK_APB2, - SYSCTL_CLOCK_ROM, - SYSCTL_CLOCK_DMA, - SYSCTL_CLOCK_AI, - SYSCTL_CLOCK_DVP, - SYSCTL_CLOCK_FFT, - SYSCTL_CLOCK_GPIO, - SYSCTL_CLOCK_SPI0, - SYSCTL_CLOCK_SPI1, - SYSCTL_CLOCK_SPI2, - SYSCTL_CLOCK_SPI3, - SYSCTL_CLOCK_I2S0, - SYSCTL_CLOCK_I2S1, - SYSCTL_CLOCK_I2S2, - SYSCTL_CLOCK_I2C0, - SYSCTL_CLOCK_I2C1, - SYSCTL_CLOCK_I2C2, - SYSCTL_CLOCK_UART1, - SYSCTL_CLOCK_UART2, - SYSCTL_CLOCK_UART3, - SYSCTL_CLOCK_AES, - SYSCTL_CLOCK_FPIOA, - SYSCTL_CLOCK_TIMER0, - SYSCTL_CLOCK_TIMER1, - SYSCTL_CLOCK_TIMER2, - SYSCTL_CLOCK_WDT0, - SYSCTL_CLOCK_WDT1, - SYSCTL_CLOCK_SHA, - SYSCTL_CLOCK_OTP, - SYSCTL_CLOCK_RTC, - SYSCTL_CLOCK_ACLK = 40, - SYSCTL_CLOCK_HCLK, - SYSCTL_CLOCK_IN0, - SYSCTL_CLOCK_MAX -} sysctl_clock_t; - -/** - * @brief System controller clock select id - */ -typedef enum _sysctl_clock_select_t -{ - SYSCTL_CLOCK_SELECT_PLL0_BYPASS, - SYSCTL_CLOCK_SELECT_PLL1_BYPASS, - SYSCTL_CLOCK_SELECT_PLL2_BYPASS, - SYSCTL_CLOCK_SELECT_PLL2, - SYSCTL_CLOCK_SELECT_ACLK, - SYSCTL_CLOCK_SELECT_SPI3, - SYSCTL_CLOCK_SELECT_TIMER0, - SYSCTL_CLOCK_SELECT_TIMER1, - SYSCTL_CLOCK_SELECT_TIMER2, - SYSCTL_CLOCK_SELECT_SPI3_SAMPLE, - SYSCTL_CLOCK_SELECT_MAX = 11 -} sysctl_clock_select_t; - -/** - * @brief System controller clock threshold id - */ -typedef enum _sysctl_threshold_t -{ - SYSCTL_THRESHOLD_ACLK, - SYSCTL_THRESHOLD_APB0, - SYSCTL_THRESHOLD_APB1, - SYSCTL_THRESHOLD_APB2, - SYSCTL_THRESHOLD_SRAM0, - SYSCTL_THRESHOLD_SRAM1, - SYSCTL_THRESHOLD_AI, - SYSCTL_THRESHOLD_DVP, - SYSCTL_THRESHOLD_ROM, - SYSCTL_THRESHOLD_SPI0, - SYSCTL_THRESHOLD_SPI1, - SYSCTL_THRESHOLD_SPI2, - SYSCTL_THRESHOLD_SPI3, - SYSCTL_THRESHOLD_TIMER0, - SYSCTL_THRESHOLD_TIMER1, - SYSCTL_THRESHOLD_TIMER2, - SYSCTL_THRESHOLD_I2S0, - SYSCTL_THRESHOLD_I2S1, - SYSCTL_THRESHOLD_I2S2, - SYSCTL_THRESHOLD_I2S0_M, - SYSCTL_THRESHOLD_I2S1_M, - SYSCTL_THRESHOLD_I2S2_M, - SYSCTL_THRESHOLD_I2C0, - SYSCTL_THRESHOLD_I2C1, - SYSCTL_THRESHOLD_I2C2, - SYSCTL_THRESHOLD_WDT0, - SYSCTL_THRESHOLD_WDT1, - SYSCTL_THRESHOLD_MAX = 28 -} sysctl_threshold_t; - -/** - * @brief System controller reset control id - */ -typedef enum _sysctl_reset_t -{ - SYSCTL_RESET_SOC, - SYSCTL_RESET_ROM, - SYSCTL_RESET_DMA, - SYSCTL_RESET_AI, - SYSCTL_RESET_DVP, - SYSCTL_RESET_FFT, - SYSCTL_RESET_GPIO, - SYSCTL_RESET_SPI0, - SYSCTL_RESET_SPI1, - SYSCTL_RESET_SPI2, - SYSCTL_RESET_SPI3, - SYSCTL_RESET_I2S0, - SYSCTL_RESET_I2S1, - SYSCTL_RESET_I2S2, - SYSCTL_RESET_I2C0, - SYSCTL_RESET_I2C1, - SYSCTL_RESET_I2C2, - SYSCTL_RESET_UART1, - SYSCTL_RESET_UART2, - SYSCTL_RESET_UART3, - SYSCTL_RESET_AES, - SYSCTL_RESET_FPIOA, - SYSCTL_RESET_TIMER0, - SYSCTL_RESET_TIMER1, - SYSCTL_RESET_TIMER2, - SYSCTL_RESET_WDT0, - SYSCTL_RESET_WDT1, - SYSCTL_RESET_SHA, - SYSCTL_RESET_RTC, - SYSCTL_RESET_MAX = 31 -} sysctl_reset_t; - -/** - * @brief System controller power bank id - */ -typedef enum _sysctl_power_bank -{ - SYSCTL_POWER_BANK0, - SYSCTL_POWER_BANK1, - SYSCTL_POWER_BANK2, - SYSCTL_POWER_BANK3, - SYSCTL_POWER_BANK4, - SYSCTL_POWER_BANK5, - SYSCTL_POWER_BANK6, - SYSCTL_POWER_BANK7, - SYSCTL_POWER_BANK_MAX, -} sysctl_power_bank_t; - -/** - * @brief System controller reset control id - */ -typedef enum _sysctl_io_power_mode -{ - SYSCTL_POWER_V33, - SYSCTL_POWER_V18 -} sysctl_io_power_mode_t; - -/** - * @brief System reset status - */ -typedef enum _sysctl_reset_enum_status -{ - SYSCTL_RESET_STATUS_HARD, - SYSCTL_RESET_STATUS_SOFT, - SYSCTL_RESET_STATUS_WDT0, - SYSCTL_RESET_STATUS_WDT1, - SYSCTL_RESET_STATUS_MAX, -} sysctl_reset_enum_status_t; - -/** - * @brief Git short commit id - * - * No. 0 Register (0x00) - */ -typedef struct _sysctl_git_id -{ - uint32_t git_id : 32; -} __attribute__((packed, aligned(4))) sysctl_git_id_t; - -/** - * @brief System clock base frequency - * - * No. 1 Register (0x04) - */ -typedef struct _sysctl_clk_freq -{ - uint32_t clk_freq : 32; -} __attribute__((packed, aligned(4))) sysctl_clk_freq_t; - -/** - * @brief PLL0 controller - * - * No. 2 Register (0x08) - */ -typedef struct _sysctl_pll0 -{ - uint32_t clkr0 : 4; - uint32_t clkf0 : 6; - uint32_t clkod0 : 4; - uint32_t bwadj0 : 6; - uint32_t pll_reset0 : 1; - uint32_t pll_pwrd0 : 1; - uint32_t pll_intfb0 : 1; - uint32_t pll_bypass0 : 1; - uint32_t pll_test0 : 1; - uint32_t pll_out_en0 : 1; - uint32_t pll_test_en : 1; - uint32_t reserved : 5; -} __attribute__((packed, aligned(4))) sysctl_pll0_t; - -/** - * @brief PLL1 controller - * - * No. 3 Register (0x0c) - */ -typedef struct _sysctl_pll1 -{ - uint32_t clkr1 : 4; - uint32_t clkf1 : 6; - uint32_t clkod1 : 4; - uint32_t bwadj1 : 6; - uint32_t pll_reset1 : 1; - uint32_t pll_pwrd1 : 1; - uint32_t pll_intfb1 : 1; - uint32_t pll_bypass1 : 1; - uint32_t pll_test1 : 1; - uint32_t pll_out_en1 : 1; - uint32_t reserved : 6; -} __attribute__((packed, aligned(4))) sysctl_pll1_t; - -/** - * @brief PLL2 controller - * - * No. 4 Register (0x10) - */ -typedef struct _sysctl_pll2 -{ - uint32_t clkr2 : 4; - uint32_t clkf2 : 6; - uint32_t clkod2 : 4; - uint32_t bwadj2 : 6; - uint32_t pll_reset2 : 1; - uint32_t pll_pwrd2 : 1; - uint32_t pll_intfb2 : 1; - uint32_t pll_bypass2 : 1; - uint32_t pll_test2 : 1; - uint32_t pll_out_en2 : 1; - uint32_t pll_ckin_sel2 : 2; - uint32_t reserved : 4; -} __attribute__((packed, aligned(4))) sysctl_pll2_t; - -/** - * @brief PLL lock tester - * - * No. 6 Register (0x18) - */ -typedef struct _sysctl_pll_lock -{ - uint32_t pll_lock0 : 2; - uint32_t pll_slip_clear0 : 1; - uint32_t test_clk_out0 : 1; - uint32_t reserved0 : 4; - uint32_t pll_lock1 : 2; - uint32_t pll_slip_clear1 : 1; - uint32_t test_clk_out1 : 1; - uint32_t reserved1 : 4; - uint32_t pll_lock2 : 2; - uint32_t pll_slip_clear2 : 1; - uint32_t test_clk_out2 : 1; - uint32_t reserved2 : 12; -} __attribute__((packed, aligned(4))) sysctl_pll_lock_t; - -/** - * @brief AXI ROM detector - * - * No. 7 Register (0x1c) - */ -typedef struct _sysctl_rom_error -{ - uint32_t rom_mul_error : 1; - uint32_t rom_one_error : 1; - uint32_t reserved : 30; -} __attribute__((packed, aligned(4))) sysctl_rom_error_t; - -/** - * @brief Clock select controller0 - * - * No. 8 Register (0x20) - */ -typedef struct _sysctl_clk_sel0 -{ - uint32_t aclk_sel : 1; - uint32_t aclk_divider_sel : 2; - uint32_t apb0_clk_sel : 3; - uint32_t apb1_clk_sel : 3; - uint32_t apb2_clk_sel : 3; - uint32_t spi3_clk_sel : 1; - uint32_t timer0_clk_sel : 1; - uint32_t timer1_clk_sel : 1; - uint32_t timer2_clk_sel : 1; - uint32_t reserved : 16; -} __attribute__((packed, aligned(4))) sysctl_clk_sel0_t; - -/** - * @brief Clock select controller1 - * - * No. 9 Register (0x24) - */ -typedef struct _sysctl_clk_sel1 -{ - uint32_t spi3_sample_clk_sel : 1; - uint32_t reserved0 : 30; - uint32_t reserved1 : 1; -} __attribute__((packed, aligned(4))) sysctl_clk_sel1_t; - -/** - * @brief Central clock enable - * - * No. 10 Register (0x28) - */ -typedef struct _sysctl_clk_en_cent -{ - uint32_t cpu_clk_en : 1; - uint32_t sram0_clk_en : 1; - uint32_t sram1_clk_en : 1; - uint32_t apb0_clk_en : 1; - uint32_t apb1_clk_en : 1; - uint32_t apb2_clk_en : 1; - uint32_t reserved : 26; -} __attribute__((packed, aligned(4))) sysctl_clk_en_cent_t; - -/** - * @brief Peripheral clock enable - * - * No. 11 Register (0x2c) - */ -typedef struct _sysctl_clk_en_peri -{ - uint32_t rom_clk_en : 1; - uint32_t dma_clk_en : 1; - uint32_t ai_clk_en : 1; - uint32_t dvp_clk_en : 1; - uint32_t fft_clk_en : 1; - uint32_t gpio_clk_en : 1; - uint32_t spi0_clk_en : 1; - uint32_t spi1_clk_en : 1; - uint32_t spi2_clk_en : 1; - uint32_t spi3_clk_en : 1; - uint32_t i2s0_clk_en : 1; - uint32_t i2s1_clk_en : 1; - uint32_t i2s2_clk_en : 1; - uint32_t i2c0_clk_en : 1; - uint32_t i2c1_clk_en : 1; - uint32_t i2c2_clk_en : 1; - uint32_t uart1_clk_en : 1; - uint32_t uart2_clk_en : 1; - uint32_t uart3_clk_en : 1; - uint32_t aes_clk_en : 1; - uint32_t fpioa_clk_en : 1; - uint32_t timer0_clk_en : 1; - uint32_t timer1_clk_en : 1; - uint32_t timer2_clk_en : 1; - uint32_t wdt0_clk_en : 1; - uint32_t wdt1_clk_en : 1; - uint32_t sha_clk_en : 1; - uint32_t otp_clk_en : 1; - uint32_t reserved : 1; - uint32_t rtc_clk_en : 1; - uint32_t reserved0 : 2; -} __attribute__((packed, aligned(4))) sysctl_clk_en_peri_t; - -/** - * @brief Soft reset ctrl - * - * No. 12 Register (0x30) - */ -typedef struct _sysctl_soft_reset -{ - uint32_t soft_reset : 1; - uint32_t reserved : 31; -} __attribute__((packed, aligned(4))) sysctl_soft_reset_t; - -/** - * @brief Peripheral reset controller - * - * No. 13 Register (0x34) - */ -typedef struct _sysctl_peri_reset -{ - uint32_t rom_reset : 1; - uint32_t dma_reset : 1; - uint32_t ai_reset : 1; - uint32_t dvp_reset : 1; - uint32_t fft_reset : 1; - uint32_t gpio_reset : 1; - uint32_t spi0_reset : 1; - uint32_t spi1_reset : 1; - uint32_t spi2_reset : 1; - uint32_t spi3_reset : 1; - uint32_t i2s0_reset : 1; - uint32_t i2s1_reset : 1; - uint32_t i2s2_reset : 1; - uint32_t i2c0_reset : 1; - uint32_t i2c1_reset : 1; - uint32_t i2c2_reset : 1; - uint32_t uart1_reset : 1; - uint32_t uart2_reset : 1; - uint32_t uart3_reset : 1; - uint32_t aes_reset : 1; - uint32_t fpioa_reset : 1; - uint32_t timer0_reset : 1; - uint32_t timer1_reset : 1; - uint32_t timer2_reset : 1; - uint32_t wdt0_reset : 1; - uint32_t wdt1_reset : 1; - uint32_t sha_reset : 1; - uint32_t reserved : 2; - uint32_t rtc_reset : 1; - uint32_t reserved0 : 2; -} __attribute__((packed, aligned(4))) sysctl_peri_reset_t; - -/** - * @brief Clock threshold controller 0 - * - * No. 14 Register (0x38) - */ -typedef struct _sysctl_clk_th0 -{ - uint32_t sram0_gclk_threshold : 4; - uint32_t sram1_gclk_threshold : 4; - uint32_t ai_gclk_threshold : 4; - uint32_t dvp_gclk_threshold : 4; - uint32_t rom_gclk_threshold : 4; - uint32_t reserved : 12; -} __attribute__((packed, aligned(4))) sysctl_clk_th0_t; - -/** - * @brief Clock threshold controller 1 - * - * No. 15 Register (0x3c) - */ -typedef struct _sysctl_clk_th1 -{ - uint32_t spi0_clk_threshold : 8; - uint32_t spi1_clk_threshold : 8; - uint32_t spi2_clk_threshold : 8; - uint32_t spi3_clk_threshold : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th1_t; - -/** - * @brief Clock threshold controller 2 - * - * No. 16 Register (0x40) - */ -typedef struct _sysctl_clk_th2 -{ - uint32_t timer0_clk_threshold : 8; - uint32_t timer1_clk_threshold : 8; - uint32_t timer2_clk_threshold : 8; - uint32_t reserved : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th2_t; - -/** - * @brief Clock threshold controller 3 - * - * No. 17 Register (0x44) - */ -typedef struct _sysctl_clk_th3 -{ - uint32_t i2s0_clk_threshold : 16; - uint32_t i2s1_clk_threshold : 16; -} __attribute__((packed, aligned(4))) sysctl_clk_th3_t; - -/** - * @brief Clock threshold controller 4 - * - * No. 18 Register (0x48) - */ -typedef struct _sysctl_clk_th4 -{ - uint32_t i2s2_clk_threshold : 16; - uint32_t i2s0_mclk_threshold : 8; - uint32_t i2s1_mclk_threshold : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th4_t; - -/** - * @brief Clock threshold controller 5 - * - * No. 19 Register (0x4c) - */ -typedef struct _sysctl_clk_th5 -{ - uint32_t i2s2_mclk_threshold : 8; - uint32_t i2c0_clk_threshold : 8; - uint32_t i2c1_clk_threshold : 8; - uint32_t i2c2_clk_threshold : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th5_t; - -/** - * @brief Clock threshold controller 6 - * - * No. 20 Register (0x50) - */ -typedef struct _sysctl_clk_th6 -{ - uint32_t wdt0_clk_threshold : 8; - uint32_t wdt1_clk_threshold : 8; - uint32_t reserved0 : 8; - uint32_t reserved1 : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th6_t; - -/** - * @brief Miscellaneous controller - * - * No. 21 Register (0x54) - */ -typedef struct _sysctl_misc -{ - uint32_t debug_sel : 6; - uint32_t reserved0 : 4; - uint32_t spi_dvp_data_enable : 1; - uint32_t reserved1 : 21; -} __attribute__((packed, aligned(4))) sysctl_misc_t; - -/** - * @brief Peripheral controller - * - * No. 22 Register (0x58) - */ -typedef struct _sysctl_peri -{ - uint32_t timer0_pause : 1; - uint32_t timer1_pause : 1; - uint32_t timer2_pause : 1; - uint32_t timer3_pause : 1; - uint32_t timer4_pause : 1; - uint32_t timer5_pause : 1; - uint32_t timer6_pause : 1; - uint32_t timer7_pause : 1; - uint32_t timer8_pause : 1; - uint32_t timer9_pause : 1; - uint32_t timer10_pause : 1; - uint32_t timer11_pause : 1; - uint32_t spi0_xip_en : 1; - uint32_t spi1_xip_en : 1; - uint32_t spi2_xip_en : 1; - uint32_t spi3_xip_en : 1; - uint32_t spi0_clk_bypass : 1; - uint32_t spi1_clk_bypass : 1; - uint32_t spi2_clk_bypass : 1; - uint32_t i2s0_clk_bypass : 1; - uint32_t i2s1_clk_bypass : 1; - uint32_t i2s2_clk_bypass : 1; - uint32_t jtag_clk_bypass : 1; - uint32_t dvp_clk_bypass : 1; - uint32_t debug_clk_bypass : 1; - uint32_t reserved0 : 1; - uint32_t reserved1 : 6; -} __attribute__((packed, aligned(4))) sysctl_peri_t; - -/** - * @brief SPI sleep controller - * - * No. 23 Register (0x5c) - */ -typedef struct _sysctl_spi_sleep -{ - uint32_t ssi0_sleep : 1; - uint32_t ssi1_sleep : 1; - uint32_t ssi2_sleep : 1; - uint32_t ssi3_sleep : 1; - uint32_t reserved : 28; -} __attribute__((packed, aligned(4))) sysctl_spi_sleep_t; - -/** - * @brief Reset source status - * - * No. 24 Register (0x60) - */ -typedef struct _sysctl_reset_status -{ - uint32_t reset_sts_clr : 1; - uint32_t pin_reset_sts : 1; - uint32_t wdt0_reset_sts : 1; - uint32_t wdt1_reset_sts : 1; - uint32_t soft_reset_sts : 1; - uint32_t reserved : 27; -} __attribute__((packed, aligned(4))) sysctl_reset_status_t; - -/** - * @brief DMA handshake selector - * - * No. 25 Register (0x64) - */ -typedef struct _sysctl_dma_sel0 -{ - uint32_t dma_sel0 : 6; - uint32_t dma_sel1 : 6; - uint32_t dma_sel2 : 6; - uint32_t dma_sel3 : 6; - uint32_t dma_sel4 : 6; - uint32_t reserved : 2; -} __attribute__((packed, aligned(4))) sysctl_dma_sel0_t; - -/** - * @brief DMA handshake selector - * - * No. 26 Register (0x68) - */ -typedef struct _sysctl_dma_sel1 -{ - uint32_t dma_sel5 : 6; - uint32_t reserved : 26; -} __attribute__((packed, aligned(4))) sysctl_dma_sel1_t; - -/** - * @brief IO Power Mode Select controller - * - * No. 27 Register (0x6c) - */ -typedef struct _sysctl_power_sel -{ - uint32_t power_mode_sel0 : 1; - uint32_t power_mode_sel1 : 1; - uint32_t power_mode_sel2 : 1; - uint32_t power_mode_sel3 : 1; - uint32_t power_mode_sel4 : 1; - uint32_t power_mode_sel5 : 1; - uint32_t power_mode_sel6 : 1; - uint32_t power_mode_sel7 : 1; - uint32_t reserved : 24; -} __attribute__((packed, aligned(4))) sysctl_power_sel_t; - -/** - * @brief System controller object - * - * The System controller is a peripheral device mapped in the - * internal memory map, discoverable in the Configuration String. - * It is responsible for low-level configuration of all system - * related peripheral device. It contain PLL controller, clock - * controller, reset controller, DMA handshake controller, SPI - * controller, timer controller, WDT controller and sleep - * controller. - */ -typedef struct _sysctl -{ - /* No. 0 (0x00): Git short commit id */ - sysctl_git_id_t git_id; - /* No. 1 (0x04): System clock base frequency */ - sysctl_clk_freq_t clk_freq; - /* No. 2 (0x08): PLL0 controller */ - sysctl_pll0_t pll0; - /* No. 3 (0x0c): PLL1 controller */ - sysctl_pll1_t pll1; - /* No. 4 (0x10): PLL2 controller */ - sysctl_pll2_t pll2; - /* No. 5 (0x14): Reserved */ - uint32_t resv5; - /* No. 6 (0x18): PLL lock tester */ - sysctl_pll_lock_t pll_lock; - /* No. 7 (0x1c): AXI ROM detector */ - sysctl_rom_error_t rom_error; - /* No. 8 (0x20): Clock select controller0 */ - sysctl_clk_sel0_t clk_sel0; - /* No. 9 (0x24): Clock select controller1 */ - sysctl_clk_sel1_t clk_sel1; - /* No. 10 (0x28): Central clock enable */ - sysctl_clk_en_cent_t clk_en_cent; - /* No. 11 (0x2c): Peripheral clock enable */ - sysctl_clk_en_peri_t clk_en_peri; - /* No. 12 (0x30): Soft reset ctrl */ - sysctl_soft_reset_t soft_reset; - /* No. 13 (0x34): Peripheral reset controller */ - sysctl_peri_reset_t peri_reset; - /* No. 14 (0x38): Clock threshold controller 0 */ - sysctl_clk_th0_t clk_th0; - /* No. 15 (0x3c): Clock threshold controller 1 */ - sysctl_clk_th1_t clk_th1; - /* No. 16 (0x40): Clock threshold controller 2 */ - sysctl_clk_th2_t clk_th2; - /* No. 17 (0x44): Clock threshold controller 3 */ - sysctl_clk_th3_t clk_th3; - /* No. 18 (0x48): Clock threshold controller 4 */ - sysctl_clk_th4_t clk_th4; - /* No. 19 (0x4c): Clock threshold controller 5 */ - sysctl_clk_th5_t clk_th5; - /* No. 20 (0x50): Clock threshold controller 6 */ - sysctl_clk_th6_t clk_th6; - /* No. 21 (0x54): Miscellaneous controller */ - sysctl_misc_t misc; - /* No. 22 (0x58): Peripheral controller */ - sysctl_peri_t peri; - /* No. 23 (0x5c): SPI sleep controller */ - sysctl_spi_sleep_t spi_sleep; - /* No. 24 (0x60): Reset source status */ - sysctl_reset_status_t reset_status; - /* No. 25 (0x64): DMA handshake selector */ - sysctl_dma_sel0_t dma_sel0; - /* No. 26 (0x68): DMA handshake selector */ - sysctl_dma_sel1_t dma_sel1; - /* No. 27 (0x6c): IO Power Mode Select controller */ - sysctl_power_sel_t power_sel; - /* No. 28 (0x70): Reserved */ - uint32_t resv28; - /* No. 29 (0x74): Reserved */ - uint32_t resv29; - /* No. 30 (0x78): Reserved */ - uint32_t resv30; - /* No. 31 (0x7c): Reserved */ - uint32_t resv31; -} __attribute__((packed, aligned(4))) sysctl_t; - -/** - * @brief Abstruct PLL struct - */ -typedef struct _sysctl_general_pll -{ - uint32_t clkr : 4; - uint32_t clkf : 6; - uint32_t clkod : 4; - uint32_t bwadj : 6; - uint32_t pll_reset : 1; - uint32_t pll_pwrd : 1; - uint32_t pll_intfb : 1; - uint32_t pll_bypass : 1; - uint32_t pll_test : 1; - uint32_t pll_out_en : 1; - uint32_t pll_ckin_sel : 2; - uint32_t reserved : 4; -} __attribute__((packed, aligned(4))) sysctl_general_pll_t; - -/** - * @brief System controller object instanse - */ -extern volatile sysctl_t *const sysctl; - - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_SYSCTL_H */ diff --git a/Kboot/src/bootloader_hi/main.c b/Kboot/src/bootloader_hi/main.c deleted file mode 100644 index bd7478c..0000000 --- a/Kboot/src/bootloader_hi/main.c +++ /dev/null @@ -1,562 +0,0 @@ -/* Copyright 2019 LoBo - * - * K210 Bootloader stage_1 - * ver. 1.4.1, 01/2020 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * ----------------------------------------------------------------------------- - * KBoot SPI Flash layout: - * ----------------------------------------------------------------------------- - * From To Length Comment - * ----------------------------------------------------------------------------- - * 0x00000000 0x00000FFF 4K bootloader stage_0 code - * 0x00001000 0x00003FFF 12K bootloader stage_1 code - * 0x00004000 0x00004FFF 4K boot configuration sector (256B used) - * 0x00005000 0x00005FFF 4K boot configuration sector BACKUP (256B used) - * 0x00006000 0x0000FFFF 40K reserved - * ----------------------------------------------------------------------------- - * 0x00010000 default application, optional, recommended - * flash_end user area, app code, file systems, data... - * ----------------------------------------------------------------------------- - */ - - -#include "spi.h" -#include "sysctl.h" -#include "fpioa.h" -#include "gpiohs.h" -#include "sha256.h" -#include "encoding.h" -#include "config.h" - -// Constants -/* - * Pin used to enter interactive mode and request the user - * to select which application to load - * Any valid and not used K210 gpio can be used except gpio#16 (0 ~ 15 & 17 ~ 47) - */ -//#define BOOT_PIN 18 -#define GPIO_KEY 2 - -#define DEFAULT_APP_ADDR 0x00010000 // default application flash address (64K) -#define APP_START_ADDR 0x80000000 // application start address in K210 SRAM -#define BOOT_CONFIG_ADDR 0x00004000 // main boot config sector in flash at 52K -#define BOOT_CONFIG_ITEMS 8 // number of handled config entries - -// boot config magic number (bits 4~31) -// flag: bit0 - active; bit1 - crc flag; bit2 - SHA flag; bit3 - check size -#define MAGIC_ID 0x5AA5D0C0 -#define MAGIC_ID_MASK 0xFFFFFFF0 -#define MAGIC_ID_FLAG 0xA55A60C0 -#define MAGIC_ID_FLAG_MASK 0xFFFFFFC0 -#define CFG_APP_FLAG_ACTIVE 0x00000001 -#define CFG_APP_FLAG_CRC32 0x00000002 -#define CFG_APP_FLAG_SHA256 0x00000004 -#define CFG_APP_FLAG_SIZE 0x00000008 - -// aplications limits -#define MIN_APP_FLASH_ADDR 0x00010000 // minimal application address in Flash: 64K -#define MAX_APP_FLASH_ADDR 0x00800000 // mmaximal application address in Flash: 8M -#define MIN_APP_FLASH_SIZE 0x00004000 // minimal application size in Flash: 16K -#define MAX_APP_FLASH_SIZE 0x00300000 // mmaximal application size in Flash: 3M - -// K210 ROM functions -typedef int rom_printf_func(const char * restrict format, ... ); -typedef int rom_getchar_func(); - -rom_printf_func *rom_printf = (rom_printf_func*)0x88001418; // fixed address in ROM -rom_printf_func *rom_printk = (rom_printf_func*)0x880016b0; // fixed address in ROM -rom_getchar_func *rom_getchar = (rom_getchar_func*)0x88008bd0; // fixed address in ROM - -// Variables - -#if FIRMWARE_SIZE -// variables used to provide mboot info to the loaded application -volatile uint32_t *ld_mbootid = (volatile uint32_t *)(APP_START_ADDR+FIRMWARE_SIZE); -volatile uint32_t *ld_address = (volatile uint32_t *)(APP_START_ADDR+FIRMWARE_SIZE+4); -volatile uint32_t *ld_size = (volatile uint32_t *)(APP_START_ADDR+FIRMWARE_SIZE+8); -#endif - -volatile sysctl_t *const sysctl = (volatile sysctl_t *)SYSCTL_BASE_ADDR; - -static uint32_t cfg_magic = 0; -static uint32_t cfg_address = 0; -static uint32_t cfg_size = 0; -static uint32_t cfg_crc = 0; -static uint8_t cfg_info[16] = "App name"; -static uint8_t available_apps[BOOT_CONFIG_ITEMS] = {0}; - -static uint64_t app_start = APP_START_ADDR; -static uint32_t app_flash_start = DEFAULT_APP_ADDR; -static uint32_t app_size = 0; -static uint8_t *app_flash_ptr = (uint8_t *)SPI3_BASE_ADDR; -static uint8_t *app_sram_ptr = (uint8_t *)APP_START_ADDR; - -static uint32_t *cfg_flash_ptr = (uint32_t *)(SPI3_BASE_ADDR+BOOT_CONFIG_ADDR); -static uint8_t *cfg_flash_bptr = (uint8_t *)(SPI3_BASE_ADDR+BOOT_CONFIG_ADDR); - -static uint32_t i = 0; -static uint32_t cfg_offset = 0; -static uint32_t offset = 0; -static uint8_t key = 0; -static uint32_t crc32; - -static uint8_t app_hash[SHA256_HASH_LEN] = {0}; -static uint8_t hash[SHA256_HASH_LEN] = {0}; -static uint8_t buffer[1024] = {0}; -static sha256_context_t context; - -static uint32_t boot_pin = 1; -static int char_in = 0; -static uint32_t print_enabled = 1; - -static uint32_t core0_sync = 0; -static uint32_t core1_sync = 0; - - -// Printing messages if interactive mode is enabled -// K210 ROM code is used for printing -#define LOG(format, ...) \ - do \ - { \ - if (print_enabled) { \ - rom_printk(format, ##__VA_ARGS__); \ - usleep(200); \ - } \ - } while(0) - - -// ==== Local functions === - -/* - * Get uint32_t value from Flash - * 8-bit Flash pionter is used, - * so the byte order must be swapped - */ -//----------------------------------------- -static uint32_t flash2uint32(uint32_t addr) -{ - uint32_t val = app_flash_ptr[addr]; - val += app_flash_ptr[addr+1] << 8; - val += app_flash_ptr[addr+2] << 16; - val += app_flash_ptr[addr+3] << 24; - return val; -} - -/* - * Get all configuration parameters - * for config sector entry at index 'i' - * into static variables - */ -//-------------------------------- -static void get_params(uint32_t i) -{ - offset = (i*8) + (cfg_offset / 4); // 32bit offset in current config sector - cfg_magic = cfg_flash_ptr[offset + 0]; - cfg_address = cfg_flash_ptr[offset + 1]; - cfg_size = cfg_flash_ptr[offset + 2]; - cfg_crc = cfg_flash_ptr[offset + 3]; - - // Get app description - offset = (i*32) + cfg_offset + 0x10; // 8bit offset in current config sector - key = cfg_flash_bptr[offset]; // dummy read needed to switch to 8bit XiP read - for (int n=0; n<16; n++) { - cfg_info[n] = cfg_flash_bptr[offset + n]; - } - cfg_info[15] = 0; -} - -/* - * Check the application's SHA256 hash - * The hash is 32 bytes long and written after the application's code - * by Kflash or other application - */ -//-------------------------- -static uint32_t app_sha256() -{ - int size = cfg_size+5; - int sz; - sha256_init(&context, size); - uint32_t idx = 0; - - while (size > 0) { - sz = (size >= 1024) ? 1024 : size; - for (int n=0; n> 1) ^ (0xEDB88320 & mask); - } - } - crc32 = ~crc; - if (crc32 != cfg_crc) { - LOG("CRC32 error, "); - return 0; - } - return 1; -} - -/* - * Check if the current application parameters - * points to the valid Kboot application - */ -//------------------------- -static uint32_t app_check() -{ - uint8_t key = app_flash_ptr[cfg_address]; // must be 0, SHA256 key NOT specified - uint32_t sz = flash2uint32(cfg_address+1); // app size - //uint32_t app_id = flash2uint32(cfg_address+7); // app ID = MAGIC_ID - - if (key != 0) return 0; - //if (app_id != MAGIC_ID) return 0; - if ((cfg_magic & CFG_APP_FLAG_SIZE) && (cfg_size != sz)) return 0; - else if (cfg_size != sz) { - LOG("app_size=%u, ", sz); - cfg_size = sz; - } - - if (cfg_magic & CFG_APP_FLAG_SHA256) { - // SHA256 check was requested, check flash data - return app_sha256(); - } - if (cfg_magic & CFG_APP_FLAG_CRC32) { - // CRC check was requested, check flash data - return app_crc32(); - } - return 1; -} - -/* - * After the 1st part of the kboot code is executed - * the execution is continued here. - * This is the first location containing the hi sram kboot code! - * ------------------------------------------------------------- - * We come here twice: running on core #0 and running on core #1 - * ------------------------------------------------------------- - */ - -//============ -int main(void) -{ - // Initialize bss data to 0, not needed as no bss data is used - /* - extern unsigned int _bss; - extern unsigned int _ebss; - unsigned int *dst; - dst = &_bss; - while(dst < &_ebss) - *dst++ = 0; - */ - - // Check the core we are running on - i = read_csr(mhartid); - //-------------------------------------------------------- - if (i != 0) { - // ============================ - // ==== Running on core #1 ==== - // ============================ - core0_sync = 1; - // wait for synchronization with core #0 - while (core1_sync == 0) { - asm("nop"); - } - - /* - * core #0 is done, the application code is transfered - * to sram at 0x80000000, continue the execution there - * - * each core has separate instruction cache - * we must clear it before continuing - */ - usleep(1000); - asm("fence"); // D-Cache; this may not be necessary, but it looks it doesn't hurt if it is executed - asm("fence.i"); // I-Cache - //asm("li a0, 1"); - asm ("jr %0" : : "r"(app_start)); - - // This should never be reached! - while (1) { - asm("nop"); - } - } - //-------------------------------------------------------- - - // ============================ - // ==== Running on core #0 ==== - // ============================ - - // wait for synchronization with core #1 - while (core0_sync == 0) { - asm("nop"); - } - - // === Printing and Flash XiP mode were initialized in stage_0 === - - // Check if interractive mode can be enabled - boot_pin = 1; - cfg_magic = cfg_flash_ptr[BOOT_CONFIG_ITEMS*8]; - print_enabled = (cfg_magic == MAGIC_ID) ? 0 : 1; - if (print_enabled) { - if ((cfg_magic & MAGIC_ID_FLAG_MASK) == MAGIC_ID_FLAG) { - // use provided pin number as boot pin - if ((cfg_magic & 0x3F) > 0) { - fpioa_set_function(cfg_magic & 0x3F, FUNC_GPIOHS2); - gpiohs_set_drive_mode(GPIO_KEY, GPIO_DM_INPUT_PULL_UP); - usleep(1000); - boot_pin = gpiohs_get_pin(GPIO_KEY); - } - } - else { - // use default pin number as boot pin - #if ((BOOT_PIN >= 0) && (BOOT_PIN < 48) && (BOOT_PIN != 16)) - fpioa_set_function(BOOT_PIN, FUNC_GPIOHS2); - gpiohs_set_drive_mode(GPIO_KEY, GPIO_DM_INPUT_PULL_UP); - usleep(1000); - boot_pin = gpiohs_get_pin(GPIO_KEY); - #endif - } - } - - LOG("\nK210 bootloader by LoBo v.1.4.3\n\n"); - - LOG("* Find applications in MAIN parameters\n"); - - // First we check the main config sector - app_flash_start = 0; - cfg_offset = 0; - - // === Read boot configuration from config sector === -check_cfg: - // Check all boot entries - for (i = 0; i < BOOT_CONFIG_ITEMS; i++) { - get_params(i); - - if ((cfg_magic & MAGIC_ID_MASK) == MAGIC_ID) { - // *** Valid configuration found - LOG(" %u: '%15s', ", i, cfg_info); - // Check if the Flash address is in range (512K ~ 8MB) - if ((cfg_address >= MIN_APP_FLASH_ADDR) && (cfg_address <= MAX_APP_FLASH_ADDR)) { - // Address valid, check if the size is in range (16K ~ 3MB) - if ((cfg_size >= MIN_APP_FLASH_SIZE) && (cfg_size <= MAX_APP_FLASH_SIZE)) { - // Valid size - LOG("@ 0x%08X, size=%u, ", cfg_address, cfg_size); - /* - * Basic check passed, now we can check the application's vilidity - * If in interractive mode, all applications are checked, - * otherwize, the application is checked only if flagged as active - */ - if ((cfg_magic & CFG_APP_FLAG_ACTIVE) || (boot_pin == 0)) { - // ** Check if valid application - if (app_check() == 0) { - LOG("App CHECK failed\n"); - continue; - } - LOG("App ok, "); - available_apps[i] = 1; - } - else { - LOG("not checked, "); - } - // ** Check if this is an active config (bit #0 set) - if ((cfg_magic & CFG_APP_FLAG_ACTIVE) == 0) { - LOG("NOT "); - } - else { - if (app_flash_start == 0) { - app_size = cfg_size; - app_flash_start = cfg_address; - } - if (boot_pin > 0) { - // Active application found and cheched and not in interractive mode - LOG("ACTIVE\n"); - break; - } - } - LOG("ACTIVE\n"); - } - else { - LOG("size Error!\n"); - } - } - else { - LOG("address Error!\n"); - } - } - } - - // check if any valid application was found - for (i = 0; i < BOOT_CONFIG_ITEMS; i++) { - if (available_apps[i]) break; - } - if ((app_flash_start == 0) && (i >= BOOT_CONFIG_ITEMS)) { - // No valid application found - if (cfg_offset == 0) { - // no valid entry found in main config sector, check the backup one - LOG("\n* Find applications in BACKUP parameters\n"); - cfg_offset = 4096; - //if (boot_pin == 0) { - // cfg_magic = cfg_flash_ptr[4096+BOOT_CONFIG_ITEMS]; - // boot_pin = (cfg_magic == MAGIC_ID) ? 1 : 0; - //} - goto check_cfg; - } - else { - LOG("\n* No app found, loading default\n"); - } - } - else if (boot_pin == 0) { - // === Interractive mode === - #if ((BOOT_PIN >= 0) && (BOOT_PIN < 48) && (BOOT_PIN != 16)) - // Check boot pin again - boot_pin = gpiohs_get_pin(GPIO_KEY); - #endif - if (boot_pin == 0) { - // ** request user to select the application to run - LOG("\nSelect the application number to load ["); - for (i = 0; i < BOOT_CONFIG_ITEMS; i++) { - if (available_apps[i]) { - LOG(" %u,", i); - } - } - LOG(" d=default ] ? "); - while (1) { - char_in = rom_getchar(); - if ((char_in == 'd') || (char_in == 'D')) { - // use default application - app_flash_start = DEFAULT_APP_ADDR; - break; - } - else { - char_in -= 0x30; - if ((char_in >= 0) && (char_in < BOOT_CONFIG_ITEMS)) { - if (available_apps[char_in]) { - get_params(char_in); - // get application's size and address in Flash - app_size = flash2uint32(cfg_address+1); - app_flash_start = cfg_address; - char_in += 0x30; - break; - } - } - char_in += 0x30; - LOG("%c? ", char_in); - } - } - LOG("%c\n\n", (char)char_in); - } - } - - #if FIRMWARE_SIZE - *ld_address = app_flash_start; - #endif - - // If default application is selected for load, get its size and check SHA hash - if (app_flash_start == 0) { - key = 1; - app_flash_start = DEFAULT_APP_ADDR; - app_size = flash2uint32(app_flash_start+1); // get app size - if ((app_size >= MIN_APP_FLASH_SIZE) && (app_size <= MAX_APP_FLASH_SIZE)) { - cfg_size = app_size; - cfg_address = app_flash_start; - // Check default application - if (app_sha256()) key = 0; - } - if (key) { - // Check failed - print_enabled = 1; - LOG("\n* Default application check failed!\n"); - LOG("* SYSTEM HALTED\n"); - while (1) { - asm ("nop"); - } - } - } - - // === Copy the application code from flash to SRAM === - #if FIRMWARE_SIZE - *ld_mbootid = MAGIC_ID; - *ld_size = app_size; - if (*ld_address == 0) { - *ld_address = app_flash_start | 0x80000000; - } - #endif - LOG("* Loading app from flash at 0x%08X (%u B)\n", app_flash_start, app_size); - - for (i=0; i < app_size; i++) { - app_sram_ptr[i] = app_flash_ptr[app_flash_start+i+5]; - } - - // === Start the application === - LOG("* Starting at 0x%08X ...\n\n", app_start); - usleep(1000); - - // Disable XIP mode - sysctl->peri.spi3_xip_en = 0; - - // === Jump to the loaded application start address === - /* - * each core has separate instruction cache - * we must clear it before continuing - */ - - core1_sync = 1; - asm("fence"); // D-Cache; this may not be necessary, but it looks it doesn't hurt if it is executed - asm("fence.i"); // I-Cache - asm ("jr %0" : : "r"(app_start)); - - // This should never be reached! - LOG("\nERROR, SYSTEM HALTED\n"); - while (1) { - asm ("nop"); - } - return 0; -} - diff --git a/Kboot/src/bootloader_hi/sha256.c b/Kboot/src/bootloader_hi/sha256.c deleted file mode 100644 index 1f3785b..0000000 --- a/Kboot/src/bootloader_hi/sha256.c +++ /dev/null @@ -1,136 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "sha256.h" -#include "sysctl.h" -#include "encoding.h" - -#define ROTL(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) -#define ROTR(x, n) (((x) >> (n)) | ((x) << (32 - (n)))) -#define BYTESWAP(x) ((ROTR((x), 8) & 0xff00ff00L) | (ROTL((x), 8) & 0x00ff00ffL)) -#define BYTESWAP64(x) byteswap64(x) - -int usleep(uint64_t usec) -{ - uint64_t cycle = read_cycle(); - uint64_t nop_all = usec * DEFAULT_CPU_CLOCK / 1000000UL; - while(1) - { - if(read_cycle() - cycle >= nop_all) - break; - } - return 0; -} - - -volatile sha256_t *const sha256 = (volatile sha256_t *)SHA256_BASE_ADDR; -static const uint8_t padding[64] = - { - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - -static inline uint64_t byteswap64(uint64_t x) -{ - uint32_t a = (uint32_t)(x >> 32); - uint32_t b = (uint32_t)x; - return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a); -} - -void sha256_init(sha256_context_t *context, size_t input_len) -{ - //sysctl_clock_enable(SYSCTL_CLOCK_SHA); - sysctl->clk_en_cent.apb0_clk_en = 1; - sysctl->clk_en_peri.sha_clk_en = 1; - //sysctl_reset(SYSCTL_RESET_SHA); - sysctl->peri_reset.sha_reset = 1; - usleep(10); - sysctl->peri_reset.sha_reset = 0; - - sha256->sha_num_reg.sha_data_cnt = (uint32_t)((input_len + SHA256_BLOCK_LEN + 8) / SHA256_BLOCK_LEN); - sha256->sha_function_reg_1.dma_en = 0x0; - sha256->sha_function_reg_0.sha_endian = SHA256_BIG_ENDIAN; - sha256->sha_function_reg_0.sha_en = ENABLE_SHA; - context->total_len = 0L; - context->buffer_len = 0L; -} - -void sha256_update(sha256_context_t *context, const void *input, size_t input_len) -{ - const uint8_t *data = input; - size_t buffer_bytes_left; - size_t bytes_to_copy; - uint32_t i; - - while(input_len) - { - buffer_bytes_left = SHA256_BLOCK_LEN - context->buffer_len; - bytes_to_copy = buffer_bytes_left; - if(bytes_to_copy > input_len) - bytes_to_copy = input_len; - memcpy(&context->buffer.bytes[context->buffer_len], data, bytes_to_copy); - context->total_len += bytes_to_copy * 8L; - context->buffer_len += bytes_to_copy; - data += bytes_to_copy; - input_len -= bytes_to_copy; - if(context->buffer_len == SHA256_BLOCK_LEN) - { - for(i = 0; i < 16; i++) - { - while(sha256->sha_function_reg_1.fifo_in_full) - ; - sha256->sha_data_in1 = context->buffer.words[i]; - } - context->buffer_len = 0L; - } - } -} - -void sha256_final(sha256_context_t *context, uint8_t *output) -{ - size_t bytes_to_pad; - size_t length_pad; - uint32_t i; - - bytes_to_pad = 120L - context->buffer_len; - if(bytes_to_pad > 64L) - bytes_to_pad -= 64L; - length_pad = BYTESWAP64(context->total_len); - sha256_update(context, padding, bytes_to_pad); - sha256_update(context, &length_pad, 8L); - while(!(sha256->sha_function_reg_0.sha_en)) - ; - if(output) - { - for(i = 0; i < SHA256_HASH_WORDS; i++) - { - *((uint32_t *)output) = sha256->sha_result[SHA256_HASH_WORDS - i - 1]; - output += 4; - } - } -} - -void sha256_hard_calculate(const uint8_t *input, size_t input_len, uint8_t *output) -{ - sha256_context_t sha; - sha256_init(&sha, input_len); - sha256_update(&sha, input, input_len); - sha256_final(&sha, output); -} diff --git a/Kboot/src/bootloader_lo/crt.S b/Kboot/src/bootloader_lo/crt.S deleted file mode 100644 index a4a1df9..0000000 --- a/Kboot/src/bootloader_lo/crt.S +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright 2019 LoBo (https://github.com/loboris) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - - -.section .text.start, "ax", @progbits -.globl _start -_start: -# Jump directly to 'main' - - j main diff --git a/Kboot/src/bootloader_lo/include/encoding.h b/Kboot/src/bootloader_lo/include/encoding.h deleted file mode 100644 index 3eebee5..0000000 --- a/Kboot/src/bootloader_lo/include/encoding.h +++ /dev/null @@ -1,1325 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001U -#define MSTATUS_SIE 0x00000002U -#define MSTATUS_HIE 0x00000004U -#define MSTATUS_MIE 0x00000008U -#define MSTATUS_UPIE 0x00000010U -#define MSTATUS_SPIE 0x00000020U -#define MSTATUS_HPIE 0x00000040U -#define MSTATUS_MPIE 0x00000080U -#define MSTATUS_SPP 0x00000100U -#define MSTATUS_HPP 0x00000600U -#define MSTATUS_MPP 0x00001800U -#define MSTATUS_FS 0x00006000U -#define MSTATUS_XS 0x00018000U -#define MSTATUS_MPRV 0x00020000U -#define MSTATUS_PUM 0x00040000U -#define MSTATUS_MXR 0x00080000U -#define MSTATUS_VM 0x1F000000U -#define MSTATUS32_SD 0x80000000U -#define MSTATUS64_SD 0x8000000000000000U - -#define SSTATUS_UIE 0x00000001U -#define SSTATUS_SIE 0x00000002U -#define SSTATUS_UPIE 0x00000010U -#define SSTATUS_SPIE 0x00000020U -#define SSTATUS_SPP 0x00000100U -#define SSTATUS_FS 0x00006000U -#define SSTATUS_XS 0x00018000U -#define SSTATUS_PUM 0x00040000U -#define SSTATUS32_SD 0x80000000U -#define SSTATUS64_SD 0x8000000000000000U - -#define DCSR_XDEBUGVER (3U << 30) -#define DCSR_NDRESET (1U << 29) -#define DCSR_FULLRESET (1U << 28) -#define DCSR_EBREAKM (1U << 15) -#define DCSR_EBREAKH (1U << 14) -#define DCSR_EBREAKS (1U << 13) -#define DCSR_EBREAKU (1U << 12) -#define DCSR_STOPCYCLE (1U << 10) -#define DCSR_STOPTIME (1U << 9) -#define DCSR_CAUSE (7U << 6) -#define DCSR_DEBUGINT (1U << 5) -#define DCSR_HALT (1U << 3) -#define DCSR_STEP (1U << 2) -#define DCSR_PRV (3U << 0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_SELECT (1U << 19) -#define MCONTROL_TIMING (1U << 18) -#define MCONTROL_ACTION (0x3fU << 12) -#define MCONTROL_CHAIN (1U << 11) -#define MCONTROL_MATCH (0xfU << 7) -#define MCONTROL_M (1U << 6) -#define MCONTROL_H (1U << 5) -#define MCONTROL_S (1U << 4) -#define MCONTROL_U (1U << 3) -#define MCONTROL_EXECUTE (1U << 2) -#define MCONTROL_STORE (1U << 1) -#define MCONTROL_LOAD (1U << 0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1U << IRQ_S_SOFT) -#define MIP_HSIP (1U << IRQ_H_SOFT) -#define MIP_MSIP (1U << IRQ_M_SOFT) -#define MIP_STIP (1U << IRQ_S_TIMER) -#define MIP_HTIP (1U << IRQ_H_TIMER) -#define MIP_MTIP (1U << IRQ_M_TIMER) -#define MIP_SEIP (1U << IRQ_S_EXT) -#define MIP_HEIP (1U << IRQ_H_EXT) -#define MIP_MEIP (1U << IRQ_M_EXT) - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000U -#define DEFAULT_NMIVEC 0x00001004U -#define DEFAULT_MTVEC 0x00001010U -#define CONFIG_STRING_ADDR 0x0000100CU -#define EXT_IO_BASE 0x40000000U -#define DRAM_BASE 0x80000000U - -/* page table entry (PTE) fields */ -#define PTE_V 0x001U /* Valid */ -#define PTE_R 0x002U /* Read */ -#define PTE_W 0x004U /* Write */ -#define PTE_X 0x008U /* Execute */ -#define PTE_U 0x010U /* User */ -#define PTE_G 0x020U /* Global */ -#define PTE_A 0x040U /* Accessed */ -#define PTE_D 0x080U /* Dirty */ -#define PTE_SOFT 0x300U /* Reserved for Software */ - -#define PTE_PPN_SHIFT 10 - -#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#if defined(__riscv) - -#if defined(__riscv64) -#define MSTATUS_SD MSTATUS64_SD -#define SSTATUS_SD SSTATUS64_SD -#define RISCV_PGLEVEL_BITS 9 -#else -#define MSTATUS_SD MSTATUS32_SD -#define SSTATUS_SD SSTATUS32_SD -#define RISCV_PGLEVEL_BITS 10 -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#if defined(__GNUC__) - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define read_time() read_csr(mtime) -#define read_cycle() read_csr(mcycle) -#define current_coreid() read_csr(mhartid) - -#endif - -#endif - -#endif - -#endif - -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63U -#define MASK_BEQ 0x707fU -#define MATCH_BNE 0x1063U -#define MASK_BNE 0x707fU -#define MATCH_BLT 0x4063U -#define MASK_BLT 0x707fU -#define MATCH_BGE 0x5063U -#define MASK_BGE 0x707fU -#define MATCH_BLTU 0x6063U -#define MASK_BLTU 0x707fU -#define MATCH_BGEU 0x7063U -#define MASK_BGEU 0x707fU -#define MATCH_JALR 0x67U -#define MASK_JALR 0x707fU -#define MATCH_JAL 0x6fU -#define MASK_JAL 0x7fU -#define MATCH_LUI 0x37U -#define MASK_LUI 0x7fU -#define MATCH_AUIPC 0x17U -#define MASK_AUIPC 0x7fU -#define MATCH_ADDI 0x13U -#define MASK_ADDI 0x707fU -#define MATCH_SLLI 0x1013U -#define MASK_SLLI 0xfc00707fU -#define MATCH_SLTI 0x2013U -#define MASK_SLTI 0x707fU -#define MATCH_SLTIU 0x3013U -#define MASK_SLTIU 0x707fU -#define MATCH_XORI 0x4013U -#define MASK_XORI 0x707fU -#define MATCH_SRLI 0x5013U -#define MASK_SRLI 0xfc00707fU -#define MATCH_SRAI 0x40005013U -#define MASK_SRAI 0xfc00707fU -#define MATCH_ORI 0x6013U -#define MASK_ORI 0x707fU -#define MATCH_ANDI 0x7013U -#define MASK_ANDI 0x707fU -#define MATCH_ADD 0x33U -#define MASK_ADD 0xfe00707fU -#define MATCH_SUB 0x40000033U -#define MASK_SUB 0xfe00707fU -#define MATCH_SLL 0x1033U -#define MASK_SLL 0xfe00707fU -#define MATCH_SLT 0x2033U -#define MASK_SLT 0xfe00707fU -#define MATCH_SLTU 0x3033U -#define MASK_SLTU 0xfe00707fU -#define MATCH_XOR 0x4033U -#define MASK_XOR 0xfe00707fU -#define MATCH_SRL 0x5033U -#define MASK_SRL 0xfe00707fU -#define MATCH_SRA 0x40005033U -#define MASK_SRA 0xfe00707fU -#define MATCH_OR 0x6033U -#define MASK_OR 0xfe00707fU -#define MATCH_AND 0x7033U -#define MASK_AND 0xfe00707fU -#define MATCH_ADDIW 0x1bU -#define MASK_ADDIW 0x707fU -#define MATCH_SLLIW 0x101bU -#define MASK_SLLIW 0xfe00707fU -#define MATCH_SRLIW 0x501bU -#define MASK_SRLIW 0xfe00707fU -#define MATCH_SRAIW 0x4000501bU -#define MASK_SRAIW 0xfe00707fU -#define MATCH_ADDW 0x3bU -#define MASK_ADDW 0xfe00707fU -#define MATCH_SUBW 0x4000003bU -#define MASK_SUBW 0xfe00707fU -#define MATCH_SLLW 0x103bU -#define MASK_SLLW 0xfe00707fU -#define MATCH_SRLW 0x503bU -#define MASK_SRLW 0xfe00707fU -#define MATCH_SRAW 0x4000503bU -#define MASK_SRAW 0xfe00707fU -#define MATCH_LB 0x3U -#define MASK_LB 0x707fU -#define MATCH_LH 0x1003U -#define MASK_LH 0x707fU -#define MATCH_LW 0x2003U -#define MASK_LW 0x707fU -#define MATCH_LD 0x3003U -#define MASK_LD 0x707fU -#define MATCH_LBU 0x4003U -#define MASK_LBU 0x707fU -#define MATCH_LHU 0x5003U -#define MASK_LHU 0x707fU -#define MATCH_LWU 0x6003U -#define MASK_LWU 0x707fU -#define MATCH_SB 0x23U -#define MASK_SB 0x707fU -#define MATCH_SH 0x1023U -#define MASK_SH 0x707fU -#define MATCH_SW 0x2023U -#define MASK_SW 0x707fU -#define MATCH_SD 0x3023U -#define MASK_SD 0x707fU -#define MATCH_FENCE 0xfU -#define MASK_FENCE 0x707fU -#define MATCH_FENCE_I 0x100fU -#define MASK_FENCE_I 0x707fU -#define MATCH_MUL 0x2000033U -#define MASK_MUL 0xfe00707fU -#define MATCH_MULH 0x2001033U -#define MASK_MULH 0xfe00707fU -#define MATCH_MULHSU 0x2002033U -#define MASK_MULHSU 0xfe00707fU -#define MATCH_MULHU 0x2003033U -#define MASK_MULHU 0xfe00707fU -#define MATCH_DIV 0x2004033U -#define MASK_DIV 0xfe00707fU -#define MATCH_DIVU 0x2005033U -#define MASK_DIVU 0xfe00707fU -#define MATCH_REM 0x2006033U -#define MASK_REM 0xfe00707fU -#define MATCH_REMU 0x2007033U -#define MASK_REMU 0xfe00707fU -#define MATCH_MULW 0x200003bU -#define MASK_MULW 0xfe00707fU -#define MATCH_DIVW 0x200403bU -#define MASK_DIVW 0xfe00707fU -#define MATCH_DIVUW 0x200503bU -#define MASK_DIVUW 0xfe00707fU -#define MATCH_REMW 0x200603bU -#define MASK_REMW 0xfe00707fU -#define MATCH_REMUW 0x200703bU -#define MASK_REMUW 0xfe00707fU -#define MATCH_AMOADD_W 0x202fU -#define MASK_AMOADD_W 0xf800707fU -#define MATCH_AMOXOR_W 0x2000202fU -#define MASK_AMOXOR_W 0xf800707fU -#define MATCH_AMOOR_W 0x4000202fU -#define MASK_AMOOR_W 0xf800707fU -#define MATCH_AMOAND_W 0x6000202fU -#define MASK_AMOAND_W 0xf800707fU -#define MATCH_AMOMIN_W 0x8000202fU -#define MASK_AMOMIN_W 0xf800707fU -#define MATCH_AMOMAX_W 0xa000202fU -#define MASK_AMOMAX_W 0xf800707fU -#define MATCH_AMOMINU_W 0xc000202fU -#define MASK_AMOMINU_W 0xf800707fU -#define MATCH_AMOMAXU_W 0xe000202fU -#define MASK_AMOMAXU_W 0xf800707fU -#define MATCH_AMOSWAP_W 0x800202fU -#define MASK_AMOSWAP_W 0xf800707fU -#define MATCH_LR_W 0x1000202fU -#define MASK_LR_W 0xf9f0707fU -#define MATCH_SC_W 0x1800202fU -#define MASK_SC_W 0xf800707fU -#define MATCH_AMOADD_D 0x302fU -#define MASK_AMOADD_D 0xf800707fU -#define MATCH_AMOXOR_D 0x2000302fU -#define MASK_AMOXOR_D 0xf800707fU -#define MATCH_AMOOR_D 0x4000302fU -#define MASK_AMOOR_D 0xf800707fU -#define MATCH_AMOAND_D 0x6000302fU -#define MASK_AMOAND_D 0xf800707fU -#define MATCH_AMOMIN_D 0x8000302fU -#define MASK_AMOMIN_D 0xf800707fU -#define MATCH_AMOMAX_D 0xa000302fU -#define MASK_AMOMAX_D 0xf800707fU -#define MATCH_AMOMINU_D 0xc000302fU -#define MASK_AMOMINU_D 0xf800707fU -#define MATCH_AMOMAXU_D 0xe000302fU -#define MASK_AMOMAXU_D 0xf800707fU -#define MATCH_AMOSWAP_D 0x800302fU -#define MASK_AMOSWAP_D 0xf800707fU -#define MATCH_LR_D 0x1000302fU -#define MASK_LR_D 0xf9f0707fU -#define MATCH_SC_D 0x1800302fU -#define MASK_SC_D 0xf800707fU -#define MATCH_ECALL 0x73U -#define MASK_ECALL 0xffffffffU -#define MATCH_EBREAK 0x100073U -#define MASK_EBREAK 0xffffffffU -#define MATCH_URET 0x200073U -#define MASK_URET 0xffffffffU -#define MATCH_SRET 0x10200073U -#define MASK_SRET 0xffffffffU -#define MATCH_HRET 0x20200073U -#define MASK_HRET 0xffffffffU -#define MATCH_MRET 0x30200073U -#define MASK_MRET 0xffffffffU -#define MATCH_DRET 0x7b200073U -#define MASK_DRET 0xffffffffU -#define MATCH_SFENCE_VM 0x10400073U -#define MASK_SFENCE_VM 0xfff07fffU -#define MATCH_WFI 0x10500073U -#define MASK_WFI 0xffffffffU -#define MATCH_CSRRW 0x1073U -#define MASK_CSRRW 0x707fU -#define MATCH_CSRRS 0x2073U -#define MASK_CSRRS 0x707fU -#define MATCH_CSRRC 0x3073U -#define MASK_CSRRC 0x707fU -#define MATCH_CSRRWI 0x5073U -#define MASK_CSRRWI 0x707fU -#define MATCH_CSRRSI 0x6073U -#define MASK_CSRRSI 0x707fU -#define MATCH_CSRRCI 0x7073U -#define MASK_CSRRCI 0x707fU -#define MATCH_FADD_S 0x53U -#define MASK_FADD_S 0xfe00007fU -#define MATCH_FSUB_S 0x8000053U -#define MASK_FSUB_S 0xfe00007fU -#define MATCH_FMUL_S 0x10000053U -#define MASK_FMUL_S 0xfe00007fU -#define MATCH_FDIV_S 0x18000053U -#define MASK_FDIV_S 0xfe00007fU -#define MATCH_FSGNJ_S 0x20000053U -#define MASK_FSGNJ_S 0xfe00707fU -#define MATCH_FSGNJN_S 0x20001053U -#define MASK_FSGNJN_S 0xfe00707fU -#define MATCH_FSGNJX_S 0x20002053U -#define MASK_FSGNJX_S 0xfe00707fU -#define MATCH_FMIN_S 0x28000053U -#define MASK_FMIN_S 0xfe00707fU -#define MATCH_FMAX_S 0x28001053U -#define MASK_FMAX_S 0xfe00707fU -#define MATCH_FSQRT_S 0x58000053U -#define MASK_FSQRT_S 0xfff0007fU -#define MATCH_FADD_D 0x2000053U -#define MASK_FADD_D 0xfe00007fU -#define MATCH_FSUB_D 0xa000053U -#define MASK_FSUB_D 0xfe00007fU -#define MATCH_FMUL_D 0x12000053U -#define MASK_FMUL_D 0xfe00007fU -#define MATCH_FDIV_D 0x1a000053U -#define MASK_FDIV_D 0xfe00007fU -#define MATCH_FSGNJ_D 0x22000053U -#define MASK_FSGNJ_D 0xfe00707fU -#define MATCH_FSGNJN_D 0x22001053U -#define MASK_FSGNJN_D 0xfe00707fU -#define MATCH_FSGNJX_D 0x22002053U -#define MASK_FSGNJX_D 0xfe00707fU -#define MATCH_FMIN_D 0x2a000053U -#define MASK_FMIN_D 0xfe00707fU -#define MATCH_FMAX_D 0x2a001053U -#define MASK_FMAX_D 0xfe00707fU -#define MATCH_FCVT_S_D 0x40100053U -#define MASK_FCVT_S_D 0xfff0007fU -#define MATCH_FCVT_D_S 0x42000053U -#define MASK_FCVT_D_S 0xfff0007fU -#define MATCH_FSQRT_D 0x5a000053U -#define MASK_FSQRT_D 0xfff0007fU -#define MATCH_FLE_S 0xa0000053U -#define MASK_FLE_S 0xfe00707fU -#define MATCH_FLT_S 0xa0001053U -#define MASK_FLT_S 0xfe00707fU -#define MATCH_FEQ_S 0xa0002053U -#define MASK_FEQ_S 0xfe00707fU -#define MATCH_FLE_D 0xa2000053U -#define MASK_FLE_D 0xfe00707fU -#define MATCH_FLT_D 0xa2001053U -#define MASK_FLT_D 0xfe00707fU -#define MATCH_FEQ_D 0xa2002053U -#define MASK_FEQ_D 0xfe00707fU -#define MATCH_FCVT_W_S 0xc0000053U -#define MASK_FCVT_W_S 0xfff0007fU -#define MATCH_FCVT_WU_S 0xc0100053U -#define MASK_FCVT_WU_S 0xfff0007fU -#define MATCH_FCVT_L_S 0xc0200053U -#define MASK_FCVT_L_S 0xfff0007fU -#define MATCH_FCVT_LU_S 0xc0300053U -#define MASK_FCVT_LU_S 0xfff0007fU -#define MATCH_FMV_X_S 0xe0000053U -#define MASK_FMV_X_S 0xfff0707fU -#define MATCH_FCLASS_S 0xe0001053U -#define MASK_FCLASS_S 0xfff0707fU -#define MATCH_FCVT_W_D 0xc2000053U -#define MASK_FCVT_W_D 0xfff0007fU -#define MATCH_FCVT_WU_D 0xc2100053U -#define MASK_FCVT_WU_D 0xfff0007fU -#define MATCH_FCVT_L_D 0xc2200053U -#define MASK_FCVT_L_D 0xfff0007fU -#define MATCH_FCVT_LU_D 0xc2300053U -#define MASK_FCVT_LU_D 0xfff0007fU -#define MATCH_FMV_X_D 0xe2000053U -#define MASK_FMV_X_D 0xfff0707fU -#define MATCH_FCLASS_D 0xe2001053U -#define MASK_FCLASS_D 0xfff0707fU -#define MATCH_FCVT_S_W 0xd0000053U -#define MASK_FCVT_S_W 0xfff0007fU -#define MATCH_FCVT_S_WU 0xd0100053U -#define MASK_FCVT_S_WU 0xfff0007fU -#define MATCH_FCVT_S_L 0xd0200053U -#define MASK_FCVT_S_L 0xfff0007fU -#define MATCH_FCVT_S_LU 0xd0300053U -#define MASK_FCVT_S_LU 0xfff0007fU -#define MATCH_FMV_S_X 0xf0000053U -#define MASK_FMV_S_X 0xfff0707fU -#define MATCH_FCVT_D_W 0xd2000053U -#define MASK_FCVT_D_W 0xfff0007fU -#define MATCH_FCVT_D_WU 0xd2100053U -#define MASK_FCVT_D_WU 0xfff0007fU -#define MATCH_FCVT_D_L 0xd2200053U -#define MASK_FCVT_D_L 0xfff0007fU -#define MATCH_FCVT_D_LU 0xd2300053U -#define MASK_FCVT_D_LU 0xfff0007fU -#define MATCH_FMV_D_X 0xf2000053U -#define MASK_FMV_D_X 0xfff0707fU -#define MATCH_FLW 0x2007U -#define MASK_FLW 0x707fU -#define MATCH_FLD 0x3007U -#define MASK_FLD 0x707fU -#define MATCH_FSW 0x2027U -#define MASK_FSW 0x707fU -#define MATCH_FSD 0x3027U -#define MASK_FSD 0x707fU -#define MATCH_FMADD_S 0x43U -#define MASK_FMADD_S 0x600007fU -#define MATCH_FMSUB_S 0x47U -#define MASK_FMSUB_S 0x600007fU -#define MATCH_FNMSUB_S 0x4bU -#define MASK_FNMSUB_S 0x600007fU -#define MATCH_FNMADD_S 0x4fU -#define MASK_FNMADD_S 0x600007fU -#define MATCH_FMADD_D 0x2000043U -#define MASK_FMADD_D 0x600007fU -#define MATCH_FMSUB_D 0x2000047U -#define MASK_FMSUB_D 0x600007fU -#define MATCH_FNMSUB_D 0x200004bU -#define MASK_FNMSUB_D 0x600007fU -#define MATCH_FNMADD_D 0x200004fU -#define MASK_FNMADD_D 0x600007fU -#define MATCH_C_NOP 0x1U -#define MASK_C_NOP 0xffffU -#define MATCH_C_ADDI16SP 0x6101U -#define MASK_C_ADDI16SP 0xef83U -#define MATCH_C_JR 0x8002U -#define MASK_C_JR 0xf07fU -#define MATCH_C_JALR 0x9002U -#define MASK_C_JALR 0xf07fU -#define MATCH_C_EBREAK 0x9002U -#define MASK_C_EBREAK 0xffffU -#define MATCH_C_LD 0x6000U -#define MASK_C_LD 0xe003U -#define MATCH_C_SD 0xe000U -#define MASK_C_SD 0xe003U -#define MATCH_C_ADDIW 0x2001U -#define MASK_C_ADDIW 0xe003U -#define MATCH_C_LDSP 0x6002U -#define MASK_C_LDSP 0xe003U -#define MATCH_C_SDSP 0xe002U -#define MASK_C_SDSP 0xe003U -#define MATCH_C_ADDI4SPN 0x0U -#define MASK_C_ADDI4SPN 0xe003U -#define MATCH_C_FLD 0x2000U -#define MASK_C_FLD 0xe003U -#define MATCH_C_LW 0x4000U -#define MASK_C_LW 0xe003U -#define MATCH_C_FLW 0x6000U -#define MASK_C_FLW 0xe003U -#define MATCH_C_FSD 0xa000U -#define MASK_C_FSD 0xe003U -#define MATCH_C_SW 0xc000U -#define MASK_C_SW 0xe003U -#define MATCH_C_FSW 0xe000U -#define MASK_C_FSW 0xe003U -#define MATCH_C_ADDI 0x1U -#define MASK_C_ADDI 0xe003U -#define MATCH_C_JAL 0x2001U -#define MASK_C_JAL 0xe003U -#define MATCH_C_LI 0x4001U -#define MASK_C_LI 0xe003U -#define MATCH_C_LUI 0x6001U -#define MASK_C_LUI 0xe003U -#define MATCH_C_SRLI 0x8001U -#define MASK_C_SRLI 0xec03U -#define MATCH_C_SRAI 0x8401U -#define MASK_C_SRAI 0xec03U -#define MATCH_C_ANDI 0x8801U -#define MASK_C_ANDI 0xec03U -#define MATCH_C_SUB 0x8c01U -#define MASK_C_SUB 0xfc63U -#define MATCH_C_XOR 0x8c21U -#define MASK_C_XOR 0xfc63U -#define MATCH_C_OR 0x8c41U -#define MASK_C_OR 0xfc63U -#define MATCH_C_AND 0x8c61U -#define MASK_C_AND 0xfc63U -#define MATCH_C_SUBW 0x9c01U -#define MASK_C_SUBW 0xfc63U -#define MATCH_C_ADDW 0x9c21U -#define MASK_C_ADDW 0xfc63U -#define MATCH_C_J 0xa001U -#define MASK_C_J 0xe003U -#define MATCH_C_BEQZ 0xc001U -#define MASK_C_BEQZ 0xe003U -#define MATCH_C_BNEZ 0xe001U -#define MASK_C_BNEZ 0xe003U -#define MATCH_C_SLLI 0x2U -#define MASK_C_SLLI 0xe003U -#define MATCH_C_FLDSP 0x2002U -#define MASK_C_FLDSP 0xe003U -#define MATCH_C_LWSP 0x4002U -#define MASK_C_LWSP 0xe003U -#define MATCH_C_FLWSP 0x6002U -#define MASK_C_FLWSP 0xe003U -#define MATCH_C_MV 0x8002U -#define MASK_C_MV 0xf003U -#define MATCH_C_ADD 0x9002U -#define MASK_C_ADD 0xf003U -#define MATCH_C_FSDSP 0xa002U -#define MASK_C_FSDSP 0xe003U -#define MATCH_C_SWSP 0xc002U -#define MASK_C_SWSP 0xe003U -#define MATCH_C_FSWSP 0xe002U -#define MASK_C_FSWSP 0xe003U -#define MATCH_CUSTOM0 0xbU -#define MASK_CUSTOM0 0x707fU -#define MATCH_CUSTOM0_RS1 0x200bU -#define MASK_CUSTOM0_RS1 0x707fU -#define MATCH_CUSTOM0_RS1_RS2 0x300bU -#define MASK_CUSTOM0_RS1_RS2 0x707fU -#define MATCH_CUSTOM0_RD 0x400bU -#define MASK_CUSTOM0_RD 0x707fU -#define MATCH_CUSTOM0_RD_RS1 0x600bU -#define MASK_CUSTOM0_RD_RS1 0x707fU -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700bU -#define MASK_CUSTOM0_RD_RS1_RS2 0x707fU -#define MATCH_CUSTOM1 0x2bU -#define MASK_CUSTOM1 0x707fU -#define MATCH_CUSTOM1_RS1 0x202bU -#define MASK_CUSTOM1_RS1 0x707fU -#define MATCH_CUSTOM1_RS1_RS2 0x302bU -#define MASK_CUSTOM1_RS1_RS2 0x707fU -#define MATCH_CUSTOM1_RD 0x402bU -#define MASK_CUSTOM1_RD 0x707fU -#define MATCH_CUSTOM1_RD_RS1 0x602bU -#define MASK_CUSTOM1_RD_RS1 0x707fU -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702bU -#define MASK_CUSTOM1_RD_RS1_RS2 0x707fU -#define MATCH_CUSTOM2 0x5bU -#define MASK_CUSTOM2 0x707fU -#define MATCH_CUSTOM2_RS1 0x205bU -#define MASK_CUSTOM2_RS1 0x707fU -#define MATCH_CUSTOM2_RS1_RS2 0x305bU -#define MASK_CUSTOM2_RS1_RS2 0x707fU -#define MATCH_CUSTOM2_RD 0x405bU -#define MASK_CUSTOM2_RD 0x707fU -#define MATCH_CUSTOM2_RD_RS1 0x605bU -#define MASK_CUSTOM2_RD_RS1 0x707fU -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705bU -#define MASK_CUSTOM2_RD_RS1_RS2 0x707fU -#define MATCH_CUSTOM3 0x7bU -#define MASK_CUSTOM3 0x707fU -#define MATCH_CUSTOM3_RS1 0x207bU -#define MASK_CUSTOM3_RS1 0x707fU -#define MATCH_CUSTOM3_RS1_RS2 0x307bU -#define MASK_CUSTOM3_RS1_RS2 0x707fU -#define MATCH_CUSTOM3_RD 0x407bU -#define MASK_CUSTOM3_RD 0x707fU -#define MATCH_CUSTOM3_RD_RS1 0x607bU -#define MASK_CUSTOM3_RD_RS1 0x707fU -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707bU -#define MASK_CUSTOM3_RD_RS1_RS2 0x707fU -#define CSR_FFLAGS 0x1U -#define CSR_FRM 0x2U -#define CSR_FCSR 0x3U -#define CSR_CYCLE 0xc00U -#define CSR_TIME 0xc01U -#define CSR_INSTRET 0xc02U -#define CSR_HPMCOUNTER3 0xc03U -#define CSR_HPMCOUNTER4 0xc04U -#define CSR_HPMCOUNTER5 0xc05U -#define CSR_HPMCOUNTER6 0xc06U -#define CSR_HPMCOUNTER7 0xc07U -#define CSR_HPMCOUNTER8 0xc08U -#define CSR_HPMCOUNTER9 0xc09U -#define CSR_HPMCOUNTER10 0xc0aU -#define CSR_HPMCOUNTER11 0xc0bU -#define CSR_HPMCOUNTER12 0xc0cU -#define CSR_HPMCOUNTER13 0xc0dU -#define CSR_HPMCOUNTER14 0xc0eU -#define CSR_HPMCOUNTER15 0xc0fU -#define CSR_HPMCOUNTER16 0xc10U -#define CSR_HPMCOUNTER17 0xc11U -#define CSR_HPMCOUNTER18 0xc12U -#define CSR_HPMCOUNTER19 0xc13U -#define CSR_HPMCOUNTER20 0xc14U -#define CSR_HPMCOUNTER21 0xc15U -#define CSR_HPMCOUNTER22 0xc16U -#define CSR_HPMCOUNTER23 0xc17U -#define CSR_HPMCOUNTER24 0xc18U -#define CSR_HPMCOUNTER25 0xc19U -#define CSR_HPMCOUNTER26 0xc1aU -#define CSR_HPMCOUNTER27 0xc1bU -#define CSR_HPMCOUNTER28 0xc1cU -#define CSR_HPMCOUNTER29 0xc1dU -#define CSR_HPMCOUNTER30 0xc1eU -#define CSR_HPMCOUNTER31 0xc1fU -#define CSR_SSTATUS 0x100U -#define CSR_SIE 0x104U -#define CSR_STVEC 0x105U -#define CSR_SSCRATCH 0x140U -#define CSR_SEPC 0x141U -#define CSR_SCAUSE 0x142U -#define CSR_SBADADDR 0x143U -#define CSR_SIP 0x144U -#define CSR_SPTBR 0x180U -#define CSR_MSTATUS 0x300U -#define CSR_MISA 0x301U -#define CSR_MEDELEG 0x302U -#define CSR_MIDELEG 0x303U -#define CSR_MIE 0x304U -#define CSR_MTVEC 0x305U -#define CSR_MSCRATCH 0x340U -#define CSR_MEPC 0x341U -#define CSR_MCAUSE 0x342U -#define CSR_MBADADDR 0x343U -#define CSR_MIP 0x344U -#define CSR_TSELECT 0x7a0U -#define CSR_TDATA1 0x7a1U -#define CSR_TDATA2 0x7a2U -#define CSR_TDATA3 0x7a3U -#define CSR_DCSR 0x7b0U -#define CSR_DPC 0x7b1U -#define CSR_DSCRATCH 0x7b2U -#define CSR_MCYCLE 0xb00U -#define CSR_MINSTRET 0xb02U -#define CSR_MHPMCOUNTER3 0xb03U -#define CSR_MHPMCOUNTER4 0xb04U -#define CSR_MHPMCOUNTER5 0xb05U -#define CSR_MHPMCOUNTER6 0xb06U -#define CSR_MHPMCOUNTER7 0xb07U -#define CSR_MHPMCOUNTER8 0xb08U -#define CSR_MHPMCOUNTER9 0xb09U -#define CSR_MHPMCOUNTER10 0xb0aU -#define CSR_MHPMCOUNTER11 0xb0bU -#define CSR_MHPMCOUNTER12 0xb0cU -#define CSR_MHPMCOUNTER13 0xb0dU -#define CSR_MHPMCOUNTER14 0xb0eU -#define CSR_MHPMCOUNTER15 0xb0fU -#define CSR_MHPMCOUNTER16 0xb10U -#define CSR_MHPMCOUNTER17 0xb11U -#define CSR_MHPMCOUNTER18 0xb12U -#define CSR_MHPMCOUNTER19 0xb13U -#define CSR_MHPMCOUNTER20 0xb14U -#define CSR_MHPMCOUNTER21 0xb15U -#define CSR_MHPMCOUNTER22 0xb16U -#define CSR_MHPMCOUNTER23 0xb17U -#define CSR_MHPMCOUNTER24 0xb18U -#define CSR_MHPMCOUNTER25 0xb19U -#define CSR_MHPMCOUNTER26 0xb1aU -#define CSR_MHPMCOUNTER27 0xb1bU -#define CSR_MHPMCOUNTER28 0xb1cU -#define CSR_MHPMCOUNTER29 0xb1dU -#define CSR_MHPMCOUNTER30 0xb1eU -#define CSR_MHPMCOUNTER31 0xb1fU -#define CSR_MUCOUNTEREN 0x320U -#define CSR_MSCOUNTEREN 0x321U -#define CSR_MHPMEVENT3 0x323U -#define CSR_MHPMEVENT4 0x324U -#define CSR_MHPMEVENT5 0x325U -#define CSR_MHPMEVENT6 0x326U -#define CSR_MHPMEVENT7 0x327U -#define CSR_MHPMEVENT8 0x328U -#define CSR_MHPMEVENT9 0x329U -#define CSR_MHPMEVENT10 0x32aU -#define CSR_MHPMEVENT11 0x32bU -#define CSR_MHPMEVENT12 0x32cU -#define CSR_MHPMEVENT13 0x32dU -#define CSR_MHPMEVENT14 0x32eU -#define CSR_MHPMEVENT15 0x32fU -#define CSR_MHPMEVENT16 0x330U -#define CSR_MHPMEVENT17 0x331U -#define CSR_MHPMEVENT18 0x332U -#define CSR_MHPMEVENT19 0x333U -#define CSR_MHPMEVENT20 0x334U -#define CSR_MHPMEVENT21 0x335U -#define CSR_MHPMEVENT22 0x336U -#define CSR_MHPMEVENT23 0x337U -#define CSR_MHPMEVENT24 0x338U -#define CSR_MHPMEVENT25 0x339U -#define CSR_MHPMEVENT26 0x33aU -#define CSR_MHPMEVENT27 0x33bU -#define CSR_MHPMEVENT28 0x33cU -#define CSR_MHPMEVENT29 0x33dU -#define CSR_MHPMEVENT30 0x33eU -#define CSR_MHPMEVENT31 0x33fU -#define CSR_MVENDORID 0xf11U -#define CSR_MARCHID 0xf12U -#define CSR_MIMPID 0xf13U -#define CSR_MHARTID 0xf14U -#define CSR_CYCLEH 0xc80U -#define CSR_TIMEH 0xc81U -#define CSR_INSTRETH 0xc82U -#define CSR_HPMCOUNTER3H 0xc83U -#define CSR_HPMCOUNTER4H 0xc84U -#define CSR_HPMCOUNTER5H 0xc85U -#define CSR_HPMCOUNTER6H 0xc86U -#define CSR_HPMCOUNTER7H 0xc87U -#define CSR_HPMCOUNTER8H 0xc88U -#define CSR_HPMCOUNTER9H 0xc89U -#define CSR_HPMCOUNTER10H 0xc8aU -#define CSR_HPMCOUNTER11H 0xc8bU -#define CSR_HPMCOUNTER12H 0xc8cU -#define CSR_HPMCOUNTER13H 0xc8dU -#define CSR_HPMCOUNTER14H 0xc8eU -#define CSR_HPMCOUNTER15H 0xc8fU -#define CSR_HPMCOUNTER16H 0xc90U -#define CSR_HPMCOUNTER17H 0xc91U -#define CSR_HPMCOUNTER18H 0xc92U -#define CSR_HPMCOUNTER19H 0xc93U -#define CSR_HPMCOUNTER20H 0xc94U -#define CSR_HPMCOUNTER21H 0xc95U -#define CSR_HPMCOUNTER22H 0xc96U -#define CSR_HPMCOUNTER23H 0xc97U -#define CSR_HPMCOUNTER24H 0xc98U -#define CSR_HPMCOUNTER25H 0xc99U -#define CSR_HPMCOUNTER26H 0xc9aU -#define CSR_HPMCOUNTER27H 0xc9bU -#define CSR_HPMCOUNTER28H 0xc9cU -#define CSR_HPMCOUNTER29H 0xc9dU -#define CSR_HPMCOUNTER30H 0xc9eU -#define CSR_HPMCOUNTER31H 0xc9fU -#define CSR_MCYCLEH 0xb80U -#define CSR_MINSTRETH 0xb82U -#define CSR_MHPMCOUNTER3H 0xb83U -#define CSR_MHPMCOUNTER4H 0xb84U -#define CSR_MHPMCOUNTER5H 0xb85U -#define CSR_MHPMCOUNTER6H 0xb86U -#define CSR_MHPMCOUNTER7H 0xb87U -#define CSR_MHPMCOUNTER8H 0xb88U -#define CSR_MHPMCOUNTER9H 0xb89U -#define CSR_MHPMCOUNTER10H 0xb8aU -#define CSR_MHPMCOUNTER11H 0xb8bU -#define CSR_MHPMCOUNTER12H 0xb8cU -#define CSR_MHPMCOUNTER13H 0xb8dU -#define CSR_MHPMCOUNTER14H 0xb8eU -#define CSR_MHPMCOUNTER15H 0xb8fU -#define CSR_MHPMCOUNTER16H 0xb90U -#define CSR_MHPMCOUNTER17H 0xb91U -#define CSR_MHPMCOUNTER18H 0xb92U -#define CSR_MHPMCOUNTER19H 0xb93U -#define CSR_MHPMCOUNTER20H 0xb94U -#define CSR_MHPMCOUNTER21H 0xb95U -#define CSR_MHPMCOUNTER22H 0xb96U -#define CSR_MHPMCOUNTER23H 0xb97U -#define CSR_MHPMCOUNTER24H 0xb98U -#define CSR_MHPMCOUNTER25H 0xb99U -#define CSR_MHPMCOUNTER26H 0xb9aU -#define CSR_MHPMCOUNTER27H 0xb9bU -#define CSR_MHPMCOUNTER28H 0xb9cU -#define CSR_MHPMCOUNTER29H 0xb9dU -#define CSR_MHPMCOUNTER30H 0xb9eU -#define CSR_MHPMCOUNTER31H 0xb9fU -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#endif -#if defined(DECLARE_INSN) -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif -#if defined(DECLARE_CSR) -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#if defined(DECLARE_CAUSE) -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -#endif diff --git a/Kboot/src/bootloader_lo/include/platform.h b/Kboot/src/bootloader_lo/include/platform.h deleted file mode 100644 index a2800a9..0000000 --- a/Kboot/src/bootloader_lo/include/platform.h +++ /dev/null @@ -1,98 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _BSP_PLATFORM_H -#define _BSP_PLATFORM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* clang-format off */ -/* Register base address */ - -/* Under Coreplex */ -#define CLINT_BASE_ADDR (0x02000000U) -#define PLIC_BASE_ADDR (0x0C000000U) - -/* Under TileLink */ -#define UARTHS_BASE_ADDR (0x38000000U) -#define GPIOHS_BASE_ADDR (0x38001000U) - -/* Under AXI 64 bit */ -#define RAM_BASE_ADDR (0x80000000U) -#define RAM_SIZE (6 * 1024 * 1024U) - -#define IO_BASE_ADDR (0x40000000U) -#define IO_SIZE (6 * 1024 * 1024U) - -#define AI_RAM_BASE_ADDR (0x80600000U) -#define AI_RAM_SIZE (2 * 1024 * 1024U) - -#define AI_IO_BASE_ADDR (0x40600000U) -#define AI_IO_SIZE (2 * 1024 * 1024U) - -#define AI_BASE_ADDR (0x40800000U) -#define AI_SIZE (12 * 1024 * 1024U) - -#define FFT_BASE_ADDR (0x42000000U) -#define FFT_SIZE (4 * 1024 * 1024U) - -#define ROM_BASE_ADDR (0x88000000U) -#define ROM_SIZE (128 * 1024U) - -/* Under AHB 32 bit */ -#define DMAC_BASE_ADDR (0x50000000U) - -/* Under APB1 32 bit */ -#define GPIO_BASE_ADDR (0x50200000U) -#define UART1_BASE_ADDR (0x50210000U) -#define UART2_BASE_ADDR (0x50220000U) -#define UART3_BASE_ADDR (0x50230000U) -#define SPI_SLAVE_BASE_ADDR (0x50240000U) -#define I2S0_BASE_ADDR (0x50250000U) -#define I2S1_BASE_ADDR (0x50260000U) -#define I2S2_BASE_ADDR (0x50270000U) -#define I2C0_BASE_ADDR (0x50280000U) -#define I2C1_BASE_ADDR (0x50290000U) -#define I2C2_BASE_ADDR (0x502A0000U) -#define FPIOA_BASE_ADDR (0x502B0000U) -#define SHA256_BASE_ADDR (0x502C0000U) -#define TIMER0_BASE_ADDR (0x502D0000U) -#define TIMER1_BASE_ADDR (0x502E0000U) -#define TIMER2_BASE_ADDR (0x502F0000U) - -/* Under APB2 32 bit */ -#define WDT0_BASE_ADDR (0x50400000U) -#define WDT1_BASE_ADDR (0x50410000U) -#define OTP_BASE_ADDR (0x50420000U) -#define DVP_BASE_ADDR (0x50430000U) -#define SYSCTL_BASE_ADDR (0x50440000U) -#define AES_BASE_ADDR (0x50450000U) -#define RTC_BASE_ADDR (0x50460000U) - - -/* Under APB3 32 bit */ -#define SPI0_BASE_ADDR (0x52000000U) -#define SPI1_BASE_ADDR (0x53000000U) -#define SPI3_BASE_ADDR (0x54000000U) - -/* clang-format on */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_PLATFORM_H */ diff --git a/Kboot/src/bootloader_lo/include/spi.h b/Kboot/src/bootloader_lo/include/spi.h deleted file mode 100644 index 2646cf8..0000000 --- a/Kboot/src/bootloader_lo/include/spi.h +++ /dev/null @@ -1,123 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_SPI_H -#define _DRIVER_SPI_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* clang-format off */ -typedef struct _spi -{ - /* SPI Control Register 0 (0x00)*/ - volatile uint32_t ctrlr0; - /* SPI Control Register 1 (0x04)*/ - volatile uint32_t ctrlr1; - /* SPI Enable Register (0x08)*/ - volatile uint32_t ssienr; - /* SPI Microwire Control Register (0x0c)*/ - volatile uint32_t mwcr; - /* SPI Slave Enable Register (0x10)*/ - volatile uint32_t ser; - /* SPI Baud Rate Select (0x14)*/ - volatile uint32_t baudr; - /* SPI Transmit FIFO Threshold Level (0x18)*/ - volatile uint32_t txftlr; - /* SPI Receive FIFO Threshold Level (0x1c)*/ - volatile uint32_t rxftlr; - /* SPI Transmit FIFO Level Register (0x20)*/ - volatile uint32_t txflr; - /* SPI Receive FIFO Level Register (0x24)*/ - volatile uint32_t rxflr; - /* SPI Status Register (0x28)*/ - volatile uint32_t sr; - /* SPI Interrupt Mask Register (0x2c)*/ - volatile uint32_t imr; - /* SPI Interrupt Status Register (0x30)*/ - volatile uint32_t isr; - /* SPI Raw Interrupt Status Register (0x34)*/ - volatile uint32_t risr; - /* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38)*/ - volatile uint32_t txoicr; - /* SPI Receive FIFO Overflow Interrupt Clear Register (0x3c)*/ - volatile uint32_t rxoicr; - /* SPI Receive FIFO Underflow Interrupt Clear Register (0x40)*/ - volatile uint32_t rxuicr; - /* SPI Multi-Master Interrupt Clear Register (0x44)*/ - volatile uint32_t msticr; - /* SPI Interrupt Clear Register (0x48)*/ - volatile uint32_t icr; - /* SPI DMA Control Register (0x4c)*/ - volatile uint32_t dmacr; - /* SPI DMA Transmit Data Level (0x50)*/ - volatile uint32_t dmatdlr; - /* SPI DMA Receive Data Level (0x54)*/ - volatile uint32_t dmardlr; - /* SPI Identification Register (0x58)*/ - volatile uint32_t idr; - /* SPI DWC_ssi component version (0x5c)*/ - volatile uint32_t ssic_version_id; - /* SPI Data Register 0-36 (0x60 -- 0xec)*/ - volatile uint32_t dr[36]; - /* SPI RX Sample Delay Register (0xf0)*/ - volatile uint32_t rx_sample_delay; - /* SPI SPI Control Register (0xf4)*/ - volatile uint32_t spi_ctrlr0; - /* reserved (0xf8)*/ - volatile uint32_t resv; - /* SPI XIP Mode bits (0xfc)*/ - volatile uint32_t xip_mode_bits; - /* SPI XIP INCR transfer opcode (0x100)*/ - volatile uint32_t xip_incr_inst; - /* SPI XIP WRAP transfer opcode (0x104)*/ - volatile uint32_t xip_wrap_inst; - /* SPI XIP Control Register (0x108)*/ - volatile uint32_t xip_ctrl; - /* SPI XIP Slave Enable Register (0x10c)*/ - volatile uint32_t xip_ser; - /* SPI XIP Receive FIFO Overflow Interrupt Clear Register (0x110)*/ - volatile uint32_t xrxoicr; - /* SPI XIP time out register for continuous transfers (0x114)*/ - volatile uint32_t xip_cnt_time_out; - volatile uint32_t endian; -} __attribute__((packed, aligned(4))) spi_t; -/* clang-format on */ - -typedef enum _spi_work_mode -{ - SPI_WORK_MODE_0, - SPI_WORK_MODE_1, - SPI_WORK_MODE_2, - SPI_WORK_MODE_3, -} spi_work_mode_t; - -typedef enum _spi_frame_format -{ - SPI_FF_STANDARD, - SPI_FF_DUAL, - SPI_FF_QUAD, - SPI_FF_OCTAL -} spi_frame_format_t; - - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_SPI_H */ diff --git a/Kboot/src/bootloader_lo/include/sysctl.h b/Kboot/src/bootloader_lo/include/sysctl.h deleted file mode 100644 index b37bd64..0000000 --- a/Kboot/src/bootloader_lo/include/sysctl.h +++ /dev/null @@ -1,886 +0,0 @@ -/* Copyright 2018 Canaan Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _DRIVER_SYSCTL_H -#define _DRIVER_SYSCTL_H - -#include -#include "platform.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#define DEFAULT_CPU_CLOCK 390000000 - - -/** - * @brief System controller register - * - * @note System controller register table - * - * | Offset | Name | Description | - * |-----------|----------------|-------------------------------------| - * | 0x00 | git_id | Git short commit id | - * | 0x04 | clk_freq | System clock base frequency | - * | 0x08 | pll0 | PLL0 controller | - * | 0x0c | pll1 | PLL1 controller | - * | 0x10 | pll2 | PLL2 controller | - * | 0x14 | resv5 | Reserved | - * | 0x18 | pll_lock | PLL lock tester | - * | 0x1c | rom_error | AXI ROM detector | - * | 0x20 | clk_sel0 | Clock select controller0 | - * | 0x24 | clk_sel1 | Clock select controller1 | - * | 0x28 | clk_en_cent | Central clock enable | - * | 0x2c | clk_en_peri | Peripheral clock enable | - * | 0x30 | soft_reset | Soft reset ctrl | - * | 0x34 | peri_reset | Peripheral reset controller | - * | 0x38 | clk_th0 | Clock threshold controller 0 | - * | 0x3c | clk_th1 | Clock threshold controller 1 | - * | 0x40 | clk_th2 | Clock threshold controller 2 | - * | 0x44 | clk_th3 | Clock threshold controller 3 | - * | 0x48 | clk_th4 | Clock threshold controller 4 | - * | 0x4c | clk_th5 | Clock threshold controller 5 | - * | 0x50 | clk_th6 | Clock threshold controller 6 | - * | 0x54 | misc | Miscellaneous controller | - * | 0x58 | peri | Peripheral controller | - * | 0x5c | spi_sleep | SPI sleep controller | - * | 0x60 | reset_status | Reset source status | - * | 0x64 | dma_sel0 | DMA handshake selector | - * | 0x68 | dma_sel1 | DMA handshake selector | - * | 0x6c | power_sel | IO Power Mode Select controller | - * | 0x70 | resv28 | Reserved | - * | 0x74 | resv29 | Reserved | - * | 0x78 | resv30 | Reserved | - * | 0x7c | resv31 | Reserved | - * - */ - -typedef enum _sysctl_pll_t -{ - SYSCTL_PLL0, - SYSCTL_PLL1, - SYSCTL_PLL2, - SYSCTL_PLL_MAX -} sysctl_pll_t; - -typedef enum _sysctl_clock_source_t -{ - SYSCTL_SOURCE_IN0, - SYSCTL_SOURCE_PLL0, - SYSCTL_SOURCE_PLL1, - SYSCTL_SOURCE_PLL2, - SYSCTL_SOURCE_ACLK, - SYSCTL_SOURCE_MAX -} sysctl_clock_source_t; - -typedef enum _sysctl_dma_channel_t -{ - SYSCTL_DMA_CHANNEL_0, - SYSCTL_DMA_CHANNEL_1, - SYSCTL_DMA_CHANNEL_2, - SYSCTL_DMA_CHANNEL_3, - SYSCTL_DMA_CHANNEL_4, - SYSCTL_DMA_CHANNEL_5, - SYSCTL_DMA_CHANNEL_MAX -} sysctl_dma_channel_t; - -typedef enum _sysctl_dma_select_t -{ - SYSCTL_DMA_SELECT_SSI0_RX_REQ, - SYSCTL_DMA_SELECT_SSI0_TX_REQ, - SYSCTL_DMA_SELECT_SSI1_RX_REQ, - SYSCTL_DMA_SELECT_SSI1_TX_REQ, - SYSCTL_DMA_SELECT_SSI2_RX_REQ, - SYSCTL_DMA_SELECT_SSI2_TX_REQ, - SYSCTL_DMA_SELECT_SSI3_RX_REQ, - SYSCTL_DMA_SELECT_SSI3_TX_REQ, - SYSCTL_DMA_SELECT_I2C0_RX_REQ, - SYSCTL_DMA_SELECT_I2C0_TX_REQ, - SYSCTL_DMA_SELECT_I2C1_RX_REQ, - SYSCTL_DMA_SELECT_I2C1_TX_REQ, - SYSCTL_DMA_SELECT_I2C2_RX_REQ, - SYSCTL_DMA_SELECT_I2C2_TX_REQ, - SYSCTL_DMA_SELECT_UART1_RX_REQ, - SYSCTL_DMA_SELECT_UART1_TX_REQ, - SYSCTL_DMA_SELECT_UART2_RX_REQ, - SYSCTL_DMA_SELECT_UART2_TX_REQ, - SYSCTL_DMA_SELECT_UART3_RX_REQ, - SYSCTL_DMA_SELECT_UART3_TX_REQ, - SYSCTL_DMA_SELECT_AES_REQ, - SYSCTL_DMA_SELECT_SHA_RX_REQ, - SYSCTL_DMA_SELECT_AI_RX_REQ, - SYSCTL_DMA_SELECT_FFT_RX_REQ, - SYSCTL_DMA_SELECT_FFT_TX_REQ, - SYSCTL_DMA_SELECT_I2S0_TX_REQ, - SYSCTL_DMA_SELECT_I2S0_RX_REQ, - SYSCTL_DMA_SELECT_I2S1_TX_REQ, - SYSCTL_DMA_SELECT_I2S1_RX_REQ, - SYSCTL_DMA_SELECT_I2S2_TX_REQ, - SYSCTL_DMA_SELECT_I2S2_RX_REQ, - SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ, - SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ, - SYSCTL_DMA_SELECT_MAX -} sysctl_dma_select_t; - -/** - * @brief System controller clock id - */ -typedef enum _sysctl_clock_t -{ - SYSCTL_CLOCK_PLL0, - SYSCTL_CLOCK_PLL1, - SYSCTL_CLOCK_PLL2, - SYSCTL_CLOCK_CPU, - SYSCTL_CLOCK_SRAM0, - SYSCTL_CLOCK_SRAM1, - SYSCTL_CLOCK_APB0, - SYSCTL_CLOCK_APB1, - SYSCTL_CLOCK_APB2, - SYSCTL_CLOCK_ROM, - SYSCTL_CLOCK_DMA, - SYSCTL_CLOCK_AI, - SYSCTL_CLOCK_DVP, - SYSCTL_CLOCK_FFT, - SYSCTL_CLOCK_GPIO, - SYSCTL_CLOCK_SPI0, - SYSCTL_CLOCK_SPI1, - SYSCTL_CLOCK_SPI2, - SYSCTL_CLOCK_SPI3, - SYSCTL_CLOCK_I2S0, - SYSCTL_CLOCK_I2S1, - SYSCTL_CLOCK_I2S2, - SYSCTL_CLOCK_I2C0, - SYSCTL_CLOCK_I2C1, - SYSCTL_CLOCK_I2C2, - SYSCTL_CLOCK_UART1, - SYSCTL_CLOCK_UART2, - SYSCTL_CLOCK_UART3, - SYSCTL_CLOCK_AES, - SYSCTL_CLOCK_FPIOA, - SYSCTL_CLOCK_TIMER0, - SYSCTL_CLOCK_TIMER1, - SYSCTL_CLOCK_TIMER2, - SYSCTL_CLOCK_WDT0, - SYSCTL_CLOCK_WDT1, - SYSCTL_CLOCK_SHA, - SYSCTL_CLOCK_OTP, - SYSCTL_CLOCK_RTC, - SYSCTL_CLOCK_ACLK = 40, - SYSCTL_CLOCK_HCLK, - SYSCTL_CLOCK_IN0, - SYSCTL_CLOCK_MAX -} sysctl_clock_t; - -/** - * @brief System controller clock select id - */ -typedef enum _sysctl_clock_select_t -{ - SYSCTL_CLOCK_SELECT_PLL0_BYPASS, - SYSCTL_CLOCK_SELECT_PLL1_BYPASS, - SYSCTL_CLOCK_SELECT_PLL2_BYPASS, - SYSCTL_CLOCK_SELECT_PLL2, - SYSCTL_CLOCK_SELECT_ACLK, - SYSCTL_CLOCK_SELECT_SPI3, - SYSCTL_CLOCK_SELECT_TIMER0, - SYSCTL_CLOCK_SELECT_TIMER1, - SYSCTL_CLOCK_SELECT_TIMER2, - SYSCTL_CLOCK_SELECT_SPI3_SAMPLE, - SYSCTL_CLOCK_SELECT_MAX = 11 -} sysctl_clock_select_t; - -/** - * @brief System controller clock threshold id - */ -typedef enum _sysctl_threshold_t -{ - SYSCTL_THRESHOLD_ACLK, - SYSCTL_THRESHOLD_APB0, - SYSCTL_THRESHOLD_APB1, - SYSCTL_THRESHOLD_APB2, - SYSCTL_THRESHOLD_SRAM0, - SYSCTL_THRESHOLD_SRAM1, - SYSCTL_THRESHOLD_AI, - SYSCTL_THRESHOLD_DVP, - SYSCTL_THRESHOLD_ROM, - SYSCTL_THRESHOLD_SPI0, - SYSCTL_THRESHOLD_SPI1, - SYSCTL_THRESHOLD_SPI2, - SYSCTL_THRESHOLD_SPI3, - SYSCTL_THRESHOLD_TIMER0, - SYSCTL_THRESHOLD_TIMER1, - SYSCTL_THRESHOLD_TIMER2, - SYSCTL_THRESHOLD_I2S0, - SYSCTL_THRESHOLD_I2S1, - SYSCTL_THRESHOLD_I2S2, - SYSCTL_THRESHOLD_I2S0_M, - SYSCTL_THRESHOLD_I2S1_M, - SYSCTL_THRESHOLD_I2S2_M, - SYSCTL_THRESHOLD_I2C0, - SYSCTL_THRESHOLD_I2C1, - SYSCTL_THRESHOLD_I2C2, - SYSCTL_THRESHOLD_WDT0, - SYSCTL_THRESHOLD_WDT1, - SYSCTL_THRESHOLD_MAX = 28 -} sysctl_threshold_t; - -/** - * @brief System controller reset control id - */ -typedef enum _sysctl_reset_t -{ - SYSCTL_RESET_SOC, - SYSCTL_RESET_ROM, - SYSCTL_RESET_DMA, - SYSCTL_RESET_AI, - SYSCTL_RESET_DVP, - SYSCTL_RESET_FFT, - SYSCTL_RESET_GPIO, - SYSCTL_RESET_SPI0, - SYSCTL_RESET_SPI1, - SYSCTL_RESET_SPI2, - SYSCTL_RESET_SPI3, - SYSCTL_RESET_I2S0, - SYSCTL_RESET_I2S1, - SYSCTL_RESET_I2S2, - SYSCTL_RESET_I2C0, - SYSCTL_RESET_I2C1, - SYSCTL_RESET_I2C2, - SYSCTL_RESET_UART1, - SYSCTL_RESET_UART2, - SYSCTL_RESET_UART3, - SYSCTL_RESET_AES, - SYSCTL_RESET_FPIOA, - SYSCTL_RESET_TIMER0, - SYSCTL_RESET_TIMER1, - SYSCTL_RESET_TIMER2, - SYSCTL_RESET_WDT0, - SYSCTL_RESET_WDT1, - SYSCTL_RESET_SHA, - SYSCTL_RESET_RTC, - SYSCTL_RESET_MAX = 31 -} sysctl_reset_t; - -/** - * @brief System controller power bank id - */ -typedef enum _sysctl_power_bank -{ - SYSCTL_POWER_BANK0, - SYSCTL_POWER_BANK1, - SYSCTL_POWER_BANK2, - SYSCTL_POWER_BANK3, - SYSCTL_POWER_BANK4, - SYSCTL_POWER_BANK5, - SYSCTL_POWER_BANK6, - SYSCTL_POWER_BANK7, - SYSCTL_POWER_BANK_MAX, -} sysctl_power_bank_t; - -/** - * @brief System controller reset control id - */ -typedef enum _sysctl_io_power_mode -{ - SYSCTL_POWER_V33, - SYSCTL_POWER_V18 -} sysctl_io_power_mode_t; - -/** - * @brief System reset status - */ -typedef enum _sysctl_reset_enum_status -{ - SYSCTL_RESET_STATUS_HARD, - SYSCTL_RESET_STATUS_SOFT, - SYSCTL_RESET_STATUS_WDT0, - SYSCTL_RESET_STATUS_WDT1, - SYSCTL_RESET_STATUS_MAX, -} sysctl_reset_enum_status_t; - -/** - * @brief Git short commit id - * - * No. 0 Register (0x00) - */ -typedef struct _sysctl_git_id -{ - uint32_t git_id : 32; -} __attribute__((packed, aligned(4))) sysctl_git_id_t; - -/** - * @brief System clock base frequency - * - * No. 1 Register (0x04) - */ -typedef struct _sysctl_clk_freq -{ - uint32_t clk_freq : 32; -} __attribute__((packed, aligned(4))) sysctl_clk_freq_t; - -/** - * @brief PLL0 controller - * - * No. 2 Register (0x08) - */ -typedef struct _sysctl_pll0 -{ - uint32_t clkr0 : 4; - uint32_t clkf0 : 6; - uint32_t clkod0 : 4; - uint32_t bwadj0 : 6; - uint32_t pll_reset0 : 1; - uint32_t pll_pwrd0 : 1; - uint32_t pll_intfb0 : 1; - uint32_t pll_bypass0 : 1; - uint32_t pll_test0 : 1; - uint32_t pll_out_en0 : 1; - uint32_t pll_test_en : 1; - uint32_t reserved : 5; -} __attribute__((packed, aligned(4))) sysctl_pll0_t; - -/** - * @brief PLL1 controller - * - * No. 3 Register (0x0c) - */ -typedef struct _sysctl_pll1 -{ - uint32_t clkr1 : 4; - uint32_t clkf1 : 6; - uint32_t clkod1 : 4; - uint32_t bwadj1 : 6; - uint32_t pll_reset1 : 1; - uint32_t pll_pwrd1 : 1; - uint32_t pll_intfb1 : 1; - uint32_t pll_bypass1 : 1; - uint32_t pll_test1 : 1; - uint32_t pll_out_en1 : 1; - uint32_t reserved : 6; -} __attribute__((packed, aligned(4))) sysctl_pll1_t; - -/** - * @brief PLL2 controller - * - * No. 4 Register (0x10) - */ -typedef struct _sysctl_pll2 -{ - uint32_t clkr2 : 4; - uint32_t clkf2 : 6; - uint32_t clkod2 : 4; - uint32_t bwadj2 : 6; - uint32_t pll_reset2 : 1; - uint32_t pll_pwrd2 : 1; - uint32_t pll_intfb2 : 1; - uint32_t pll_bypass2 : 1; - uint32_t pll_test2 : 1; - uint32_t pll_out_en2 : 1; - uint32_t pll_ckin_sel2 : 2; - uint32_t reserved : 4; -} __attribute__((packed, aligned(4))) sysctl_pll2_t; - -/** - * @brief PLL lock tester - * - * No. 6 Register (0x18) - */ -typedef struct _sysctl_pll_lock -{ - uint32_t pll_lock0 : 2; - uint32_t pll_slip_clear0 : 1; - uint32_t test_clk_out0 : 1; - uint32_t reserved0 : 4; - uint32_t pll_lock1 : 2; - uint32_t pll_slip_clear1 : 1; - uint32_t test_clk_out1 : 1; - uint32_t reserved1 : 4; - uint32_t pll_lock2 : 2; - uint32_t pll_slip_clear2 : 1; - uint32_t test_clk_out2 : 1; - uint32_t reserved2 : 12; -} __attribute__((packed, aligned(4))) sysctl_pll_lock_t; - -/** - * @brief AXI ROM detector - * - * No. 7 Register (0x1c) - */ -typedef struct _sysctl_rom_error -{ - uint32_t rom_mul_error : 1; - uint32_t rom_one_error : 1; - uint32_t reserved : 30; -} __attribute__((packed, aligned(4))) sysctl_rom_error_t; - -/** - * @brief Clock select controller0 - * - * No. 8 Register (0x20) - */ -typedef struct _sysctl_clk_sel0 -{ - uint32_t aclk_sel : 1; - uint32_t aclk_divider_sel : 2; - uint32_t apb0_clk_sel : 3; - uint32_t apb1_clk_sel : 3; - uint32_t apb2_clk_sel : 3; - uint32_t spi3_clk_sel : 1; - uint32_t timer0_clk_sel : 1; - uint32_t timer1_clk_sel : 1; - uint32_t timer2_clk_sel : 1; - uint32_t reserved : 16; -} __attribute__((packed, aligned(4))) sysctl_clk_sel0_t; - -/** - * @brief Clock select controller1 - * - * No. 9 Register (0x24) - */ -typedef struct _sysctl_clk_sel1 -{ - uint32_t spi3_sample_clk_sel : 1; - uint32_t reserved0 : 30; - uint32_t reserved1 : 1; -} __attribute__((packed, aligned(4))) sysctl_clk_sel1_t; - -/** - * @brief Central clock enable - * - * No. 10 Register (0x28) - */ -typedef struct _sysctl_clk_en_cent -{ - uint32_t cpu_clk_en : 1; - uint32_t sram0_clk_en : 1; - uint32_t sram1_clk_en : 1; - uint32_t apb0_clk_en : 1; - uint32_t apb1_clk_en : 1; - uint32_t apb2_clk_en : 1; - uint32_t reserved : 26; -} __attribute__((packed, aligned(4))) sysctl_clk_en_cent_t; - -/** - * @brief Peripheral clock enable - * - * No. 11 Register (0x2c) - */ -typedef struct _sysctl_clk_en_peri -{ - uint32_t rom_clk_en : 1; - uint32_t dma_clk_en : 1; - uint32_t ai_clk_en : 1; - uint32_t dvp_clk_en : 1; - uint32_t fft_clk_en : 1; - uint32_t gpio_clk_en : 1; - uint32_t spi0_clk_en : 1; - uint32_t spi1_clk_en : 1; - uint32_t spi2_clk_en : 1; - uint32_t spi3_clk_en : 1; - uint32_t i2s0_clk_en : 1; - uint32_t i2s1_clk_en : 1; - uint32_t i2s2_clk_en : 1; - uint32_t i2c0_clk_en : 1; - uint32_t i2c1_clk_en : 1; - uint32_t i2c2_clk_en : 1; - uint32_t uart1_clk_en : 1; - uint32_t uart2_clk_en : 1; - uint32_t uart3_clk_en : 1; - uint32_t aes_clk_en : 1; - uint32_t fpioa_clk_en : 1; - uint32_t timer0_clk_en : 1; - uint32_t timer1_clk_en : 1; - uint32_t timer2_clk_en : 1; - uint32_t wdt0_clk_en : 1; - uint32_t wdt1_clk_en : 1; - uint32_t sha_clk_en : 1; - uint32_t otp_clk_en : 1; - uint32_t reserved : 1; - uint32_t rtc_clk_en : 1; - uint32_t reserved0 : 2; -} __attribute__((packed, aligned(4))) sysctl_clk_en_peri_t; - -/** - * @brief Soft reset ctrl - * - * No. 12 Register (0x30) - */ -typedef struct _sysctl_soft_reset -{ - uint32_t soft_reset : 1; - uint32_t reserved : 31; -} __attribute__((packed, aligned(4))) sysctl_soft_reset_t; - -/** - * @brief Peripheral reset controller - * - * No. 13 Register (0x34) - */ -typedef struct _sysctl_peri_reset -{ - uint32_t rom_reset : 1; - uint32_t dma_reset : 1; - uint32_t ai_reset : 1; - uint32_t dvp_reset : 1; - uint32_t fft_reset : 1; - uint32_t gpio_reset : 1; - uint32_t spi0_reset : 1; - uint32_t spi1_reset : 1; - uint32_t spi2_reset : 1; - uint32_t spi3_reset : 1; - uint32_t i2s0_reset : 1; - uint32_t i2s1_reset : 1; - uint32_t i2s2_reset : 1; - uint32_t i2c0_reset : 1; - uint32_t i2c1_reset : 1; - uint32_t i2c2_reset : 1; - uint32_t uart1_reset : 1; - uint32_t uart2_reset : 1; - uint32_t uart3_reset : 1; - uint32_t aes_reset : 1; - uint32_t fpioa_reset : 1; - uint32_t timer0_reset : 1; - uint32_t timer1_reset : 1; - uint32_t timer2_reset : 1; - uint32_t wdt0_reset : 1; - uint32_t wdt1_reset : 1; - uint32_t sha_reset : 1; - uint32_t reserved : 2; - uint32_t rtc_reset : 1; - uint32_t reserved0 : 2; -} __attribute__((packed, aligned(4))) sysctl_peri_reset_t; - -/** - * @brief Clock threshold controller 0 - * - * No. 14 Register (0x38) - */ -typedef struct _sysctl_clk_th0 -{ - uint32_t sram0_gclk_threshold : 4; - uint32_t sram1_gclk_threshold : 4; - uint32_t ai_gclk_threshold : 4; - uint32_t dvp_gclk_threshold : 4; - uint32_t rom_gclk_threshold : 4; - uint32_t reserved : 12; -} __attribute__((packed, aligned(4))) sysctl_clk_th0_t; - -/** - * @brief Clock threshold controller 1 - * - * No. 15 Register (0x3c) - */ -typedef struct _sysctl_clk_th1 -{ - uint32_t spi0_clk_threshold : 8; - uint32_t spi1_clk_threshold : 8; - uint32_t spi2_clk_threshold : 8; - uint32_t spi3_clk_threshold : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th1_t; - -/** - * @brief Clock threshold controller 2 - * - * No. 16 Register (0x40) - */ -typedef struct _sysctl_clk_th2 -{ - uint32_t timer0_clk_threshold : 8; - uint32_t timer1_clk_threshold : 8; - uint32_t timer2_clk_threshold : 8; - uint32_t reserved : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th2_t; - -/** - * @brief Clock threshold controller 3 - * - * No. 17 Register (0x44) - */ -typedef struct _sysctl_clk_th3 -{ - uint32_t i2s0_clk_threshold : 16; - uint32_t i2s1_clk_threshold : 16; -} __attribute__((packed, aligned(4))) sysctl_clk_th3_t; - -/** - * @brief Clock threshold controller 4 - * - * No. 18 Register (0x48) - */ -typedef struct _sysctl_clk_th4 -{ - uint32_t i2s2_clk_threshold : 16; - uint32_t i2s0_mclk_threshold : 8; - uint32_t i2s1_mclk_threshold : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th4_t; - -/** - * @brief Clock threshold controller 5 - * - * No. 19 Register (0x4c) - */ -typedef struct _sysctl_clk_th5 -{ - uint32_t i2s2_mclk_threshold : 8; - uint32_t i2c0_clk_threshold : 8; - uint32_t i2c1_clk_threshold : 8; - uint32_t i2c2_clk_threshold : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th5_t; - -/** - * @brief Clock threshold controller 6 - * - * No. 20 Register (0x50) - */ -typedef struct _sysctl_clk_th6 -{ - uint32_t wdt0_clk_threshold : 8; - uint32_t wdt1_clk_threshold : 8; - uint32_t reserved0 : 8; - uint32_t reserved1 : 8; -} __attribute__((packed, aligned(4))) sysctl_clk_th6_t; - -/** - * @brief Miscellaneous controller - * - * No. 21 Register (0x54) - */ -typedef struct _sysctl_misc -{ - uint32_t debug_sel : 6; - uint32_t reserved0 : 4; - uint32_t spi_dvp_data_enable : 1; - uint32_t reserved1 : 21; -} __attribute__((packed, aligned(4))) sysctl_misc_t; - -/** - * @brief Peripheral controller - * - * No. 22 Register (0x58) - */ -typedef struct _sysctl_peri -{ - uint32_t timer0_pause : 1; - uint32_t timer1_pause : 1; - uint32_t timer2_pause : 1; - uint32_t timer3_pause : 1; - uint32_t timer4_pause : 1; - uint32_t timer5_pause : 1; - uint32_t timer6_pause : 1; - uint32_t timer7_pause : 1; - uint32_t timer8_pause : 1; - uint32_t timer9_pause : 1; - uint32_t timer10_pause : 1; - uint32_t timer11_pause : 1; - uint32_t spi0_xip_en : 1; - uint32_t spi1_xip_en : 1; - uint32_t spi2_xip_en : 1; - uint32_t spi3_xip_en : 1; - uint32_t spi0_clk_bypass : 1; - uint32_t spi1_clk_bypass : 1; - uint32_t spi2_clk_bypass : 1; - uint32_t i2s0_clk_bypass : 1; - uint32_t i2s1_clk_bypass : 1; - uint32_t i2s2_clk_bypass : 1; - uint32_t jtag_clk_bypass : 1; - uint32_t dvp_clk_bypass : 1; - uint32_t debug_clk_bypass : 1; - uint32_t reserved0 : 1; - uint32_t reserved1 : 6; -} __attribute__((packed, aligned(4))) sysctl_peri_t; - -/** - * @brief SPI sleep controller - * - * No. 23 Register (0x5c) - */ -typedef struct _sysctl_spi_sleep -{ - uint32_t ssi0_sleep : 1; - uint32_t ssi1_sleep : 1; - uint32_t ssi2_sleep : 1; - uint32_t ssi3_sleep : 1; - uint32_t reserved : 28; -} __attribute__((packed, aligned(4))) sysctl_spi_sleep_t; - -/** - * @brief Reset source status - * - * No. 24 Register (0x60) - */ -typedef struct _sysctl_reset_status -{ - uint32_t reset_sts_clr : 1; - uint32_t pin_reset_sts : 1; - uint32_t wdt0_reset_sts : 1; - uint32_t wdt1_reset_sts : 1; - uint32_t soft_reset_sts : 1; - uint32_t reserved : 27; -} __attribute__((packed, aligned(4))) sysctl_reset_status_t; - -/** - * @brief DMA handshake selector - * - * No. 25 Register (0x64) - */ -typedef struct _sysctl_dma_sel0 -{ - uint32_t dma_sel0 : 6; - uint32_t dma_sel1 : 6; - uint32_t dma_sel2 : 6; - uint32_t dma_sel3 : 6; - uint32_t dma_sel4 : 6; - uint32_t reserved : 2; -} __attribute__((packed, aligned(4))) sysctl_dma_sel0_t; - -/** - * @brief DMA handshake selector - * - * No. 26 Register (0x68) - */ -typedef struct _sysctl_dma_sel1 -{ - uint32_t dma_sel5 : 6; - uint32_t reserved : 26; -} __attribute__((packed, aligned(4))) sysctl_dma_sel1_t; - -/** - * @brief IO Power Mode Select controller - * - * No. 27 Register (0x6c) - */ -typedef struct _sysctl_power_sel -{ - uint32_t power_mode_sel0 : 1; - uint32_t power_mode_sel1 : 1; - uint32_t power_mode_sel2 : 1; - uint32_t power_mode_sel3 : 1; - uint32_t power_mode_sel4 : 1; - uint32_t power_mode_sel5 : 1; - uint32_t power_mode_sel6 : 1; - uint32_t power_mode_sel7 : 1; - uint32_t reserved : 24; -} __attribute__((packed, aligned(4))) sysctl_power_sel_t; - -/** - * @brief System controller object - * - * The System controller is a peripheral device mapped in the - * internal memory map, discoverable in the Configuration String. - * It is responsible for low-level configuration of all system - * related peripheral device. It contain PLL controller, clock - * controller, reset controller, DMA handshake controller, SPI - * controller, timer controller, WDT controller and sleep - * controller. - */ -typedef struct _sysctl -{ - /* No. 0 (0x00): Git short commit id */ - sysctl_git_id_t git_id; - /* No. 1 (0x04): System clock base frequency */ - sysctl_clk_freq_t clk_freq; - /* No. 2 (0x08): PLL0 controller */ - sysctl_pll0_t pll0; - /* No. 3 (0x0c): PLL1 controller */ - sysctl_pll1_t pll1; - /* No. 4 (0x10): PLL2 controller */ - sysctl_pll2_t pll2; - /* No. 5 (0x14): Reserved */ - uint32_t resv5; - /* No. 6 (0x18): PLL lock tester */ - sysctl_pll_lock_t pll_lock; - /* No. 7 (0x1c): AXI ROM detector */ - sysctl_rom_error_t rom_error; - /* No. 8 (0x20): Clock select controller0 */ - sysctl_clk_sel0_t clk_sel0; - /* No. 9 (0x24): Clock select controller1 */ - sysctl_clk_sel1_t clk_sel1; - /* No. 10 (0x28): Central clock enable */ - sysctl_clk_en_cent_t clk_en_cent; - /* No. 11 (0x2c): Peripheral clock enable */ - sysctl_clk_en_peri_t clk_en_peri; - /* No. 12 (0x30): Soft reset ctrl */ - sysctl_soft_reset_t soft_reset; - /* No. 13 (0x34): Peripheral reset controller */ - sysctl_peri_reset_t peri_reset; - /* No. 14 (0x38): Clock threshold controller 0 */ - sysctl_clk_th0_t clk_th0; - /* No. 15 (0x3c): Clock threshold controller 1 */ - sysctl_clk_th1_t clk_th1; - /* No. 16 (0x40): Clock threshold controller 2 */ - sysctl_clk_th2_t clk_th2; - /* No. 17 (0x44): Clock threshold controller 3 */ - sysctl_clk_th3_t clk_th3; - /* No. 18 (0x48): Clock threshold controller 4 */ - sysctl_clk_th4_t clk_th4; - /* No. 19 (0x4c): Clock threshold controller 5 */ - sysctl_clk_th5_t clk_th5; - /* No. 20 (0x50): Clock threshold controller 6 */ - sysctl_clk_th6_t clk_th6; - /* No. 21 (0x54): Miscellaneous controller */ - sysctl_misc_t misc; - /* No. 22 (0x58): Peripheral controller */ - sysctl_peri_t peri; - /* No. 23 (0x5c): SPI sleep controller */ - sysctl_spi_sleep_t spi_sleep; - /* No. 24 (0x60): Reset source status */ - sysctl_reset_status_t reset_status; - /* No. 25 (0x64): DMA handshake selector */ - sysctl_dma_sel0_t dma_sel0; - /* No. 26 (0x68): DMA handshake selector */ - sysctl_dma_sel1_t dma_sel1; - /* No. 27 (0x6c): IO Power Mode Select controller */ - sysctl_power_sel_t power_sel; - /* No. 28 (0x70): Reserved */ - uint32_t resv28; - /* No. 29 (0x74): Reserved */ - uint32_t resv29; - /* No. 30 (0x78): Reserved */ - uint32_t resv30; - /* No. 31 (0x7c): Reserved */ - uint32_t resv31; -} __attribute__((packed, aligned(4))) sysctl_t; - -/** - * @brief Abstruct PLL struct - */ -typedef struct _sysctl_general_pll -{ - uint32_t clkr : 4; - uint32_t clkf : 6; - uint32_t clkod : 4; - uint32_t bwadj : 6; - uint32_t pll_reset : 1; - uint32_t pll_pwrd : 1; - uint32_t pll_intfb : 1; - uint32_t pll_bypass : 1; - uint32_t pll_test : 1; - uint32_t pll_out_en : 1; - uint32_t pll_ckin_sel : 2; - uint32_t reserved : 4; -} __attribute__((packed, aligned(4))) sysctl_general_pll_t; - -/** - * @brief System controller object instanse - */ -extern volatile sysctl_t *const sysctl; - - -#ifdef __cplusplus -} -#endif - -#endif /* _DRIVER_SYSCTL_H */ diff --git a/Kboot/src/bootloader_lo/main.c b/Kboot/src/bootloader_lo/main.c deleted file mode 100644 index 2897bce..0000000 --- a/Kboot/src/bootloader_lo/main.c +++ /dev/null @@ -1,191 +0,0 @@ -/* Copyright 2019 LoBo - * - * K210 Bootloader stage_0 - * ver. 1.4.1, 01/2020 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * ----------------------------------------------------------------------------- - * KBoot SPI Flash layout: - * ----------------------------------------------------------------------------- - * From To Length Comment - * ----------------------------------------------------------------------------- - * 0x00000000 0x00000FFF 4K bootloader stage_0 code - * 0x00001000 0x00003FFF 12K bootloader stage_1 code - * 0x00004000 0x00004FFF 4K boot configuration sector (256B used) - * 0x00005000 0x00005FFF 4K boot configuration sector BACKUP (256B used) - * 0x00006000 0x0000FFFF 40K reserved - * ----------------------------------------------------------------------------- - * 0x00010000 default application, optional, recommended - * flash_end user area, app code, file systems, data... - * ----------------------------------------------------------------------------- - */ - - -#include "spi.h" -#include "sysctl.h" -#include "encoding.h" - -// Constants - -#define BOOTHI_FLASH_ADDR 0x00001005 // stage_1 bootloader code Flash address -#define BOOTHI_SRAM_ADDR 0x805E0000 // stage_1 bootloader code SRAM address -#define BOOTHI_SIZE 0x00003000 // stage_1 bootloader code size (max) - -// K210 ROM functions -typedef int rom_print_func(const char * restrict format, ... ); -rom_print_func *rom_printf = (rom_print_func*)0x88001418; // fixed address in ROM -rom_print_func *rom_printk = (rom_print_func*)0x880016b0; // fixed address in ROM - -// Variables -volatile sysctl_t *const sysctl = (volatile sysctl_t *)SYSCTL_BASE_ADDR; -static volatile spi_t *spi_handle = (volatile spi_t *)SPI3_BASE_ADDR; - -static uint64_t boothi_start = BOOTHI_SRAM_ADDR; -static uint8_t *boothi_flash_ptr = (uint8_t *)SPI3_BASE_ADDR+BOOTHI_FLASH_ADDR; -static uint8_t *boothi_sram_ptr = (uint8_t *)BOOTHI_SRAM_ADDR; -static uint32_t i = 0; -static uint32_t core0_sync = 0; -static uint32_t core1_sync = 0; - -/* - * After the K210 is reset the 'booltloder_lo.bin' code is loaded from SPI Flash - * to SRAM address 0x80000000 by ROM code and executed. - * This is the first location containing the K210 code! - * ------------------------------------------------------------- - * We come here twice: running on core #0 and running on core #1 - * ------------------------------------------------------------- - */ - -//============ -int main(void) -{ - // Initialize bss data to 0, not needed as no bss data is used - /* - extern unsigned int _bss; - extern unsigned int _ebss; - unsigned int *dst; - dst = &_bss; - while(dst < &_ebss) - *dst++ = 0; - */ - - // Check the core we are running on - i = read_csr(mhartid); - //--------------------------------------------------------- - if (i != 0) { - // ============================ - // ==== Running on core #1 ==== - // ============================ - core0_sync = 1; - // wait for synchronization with core #0 - while (core1_sync == 0) { - asm("nop"); - } - /* - * core #0 is done, the 2nd part of kboot is transfered - * to the high sram, continue the execution there - * - * each core has separate instruction cache - * we must clear it before continuing - */ - asm("fence"); // D-Cache; this may not be necessary, but it looks it doesn't hurt if it is executed - asm("fence.i"); // I-Cache - // continue at 2nd part of kboot at high sram - asm ("jr %0" : : "r"(boothi_start)); - - // This should never be reached! - while (1) { - asm("nop"); - } - } - //--------------------------------------------------------- - - // ============================ - // ==== Running on core #0 ==== - // ============================ - - // Without this command every character is printed twice (why !?) - rom_printf(NULL); - // wait for synchronization with core #1 - while (core0_sync == 0) { - asm("nop"); - } - - // ---------------------------------------------------------------------------------------------- - // === Initialize SPI Flash driver === - // spi clock init (SPI3 clock source is PLL0/2, 390 MHz) - sysctl->clk_sel0.spi3_clk_sel = 1; - sysctl->clk_en_peri.spi3_clk_en = 1; - sysctl->clk_th1.spi3_clk_threshold = 0; - - // spi3 init - // sets spi clock to 43.333333 MHz - spi_handle->baudr = 9; - spi_handle->imr = 0x00; - spi_handle->dmacr = 0x00; - spi_handle->dmatdlr = 0x10; - spi_handle->dmardlr = 0x00; - spi_handle->ser = 0x00; - spi_handle->ssienr = 0x00; - spi_handle->ctrlr0 = (SPI_WORK_MODE_0 << 8) | (SPI_FF_QUAD << 22) | (7 << 0); - spi_handle->spi_ctrlr0 = 0; - spi_handle->endian = 0; - - // Enable XIP mode - spi_handle->xip_ctrl = (0x01 << 29) | (0x02 << 26) | (0x01 << 23) | (0x01 << 22) | (0x04 << 13) | - (0x01 << 12) | (0x02 << 9) | (0x06 << 4) | (0x01 << 2) | 0x02; - spi_handle->xip_incr_inst = 0xEB; - spi_handle->xip_mode_bits = 0x00; - spi_handle->xip_ser = 0x01; - spi_handle->ssienr = 0x01; - sysctl->peri.spi3_xip_en = 1; - // ---------------------------------------------------------------------------------------------- - - // ========================================================================== - // === Copy the 2nd part of kboot code from flash to SRAM at high address === - // ========================================================================== - for (i = 0; i < BOOTHI_SIZE; i++) { - *boothi_sram_ptr++ = *boothi_flash_ptr++; - } - - // === JUMP to stage_1 code start === - // Leave XIP mode enabled - /* - * each core has separate instruction cache - * we must clear it before continuing - * Quote: - The FENCE.I instruction is used to synchronize the instruction and data streams. - RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches - on a RISC-V hart until that hart executes a FENCE.I instruction. - A FENCE.I instruction ensures that a subsequent instruction fetch on a RISC-V hart - will see any previous data stores already visible to the same RISC-V hart. - FENCE.I does not ensure that other RISC-V harts’ instruction fetches will - observe the local hart’s stores in a multiprocessor system. - To make a store to instruction memory visible to all RISC-V harts, - the writing hart has to execute a data FENCE before requesting that all remote RISC-V harts execute a FENCE.I. - */ - - core1_sync = 1; - asm("fence"); // D-Cache; this may not be necessary, but it looks it doesn't hurt if it is executed - asm("fence.i"); // I-Cache - asm ("jr %0" : : "r"(boothi_start)); - - // This should never be reached! - while (1) { - asm("nop"); - } - return 0; -} diff --git a/docker/run.sh b/docker/run.sh index 1a85f6d..5a34ee0 100755 --- a/docker/run.sh +++ b/docker/run.sh @@ -1,3 +1,3 @@ -#! /opt/local/bin/bash +#! /bin/bash -docker run -it --rm -v $(PWD)/..:/src k210mpy bash +docker run -it --rm -v $(pwd)/..:/src k210mpy bash diff --git a/k210-freertos/.config b/k210-freertos/.config index 2318277..4fe8d31 100644 --- a/k210-freertos/.config +++ b/k210-freertos/.config @@ -12,7 +12,8 @@ CONFIG_FIRMWARE_SIZE_TYPE=2 CONFIG_FIRMWARE_SIZE_3_MB=y # CONFIG_FIRMWARE_SIZE_3_5_MB is not set CONFIG_MICROPY_K210_KPU_USED=y -# CONFIG_MICROPY_USE_OTA is not set +CONFIG_MICROPY_USE_OTA=y +CONFIG_MICRO_PY_MBOOT_PIN=17 CONFIG_MICRO_PY_FREE_RTOS_RESERVED=768 CONFIG_MICROPY_HW_BOARD_NAME="Sipeed_board" CONFIG_MICROPY_HW_MCU_NAME="Kendryte-K210" @@ -57,11 +58,11 @@ CONFIG_MICRO_PY_SD_CS=29 # CONFIG_MICROPY_PY_USE_SQLITE is not set CONFIG_MICROPY_USE_DISPLAY=y CONFIG_MICROPY_USE_TFT=y -CONFIG_MICROPY_USE_EPD=y +# CONFIG_MICROPY_USE_EPD is not set CONFIG_MICROPY_USE_CAMERA=y CONFIG_MICROPY_PY_USE_GSM=y CONFIG_MICROPY_PY_USE_WIFI=y -# CONFIG_MICROPY_PY_USE_ESP32 is not set +CONFIG_MICROPY_PY_USE_ESP32=y CONFIG_MICROPY_PY_USE_MQTT=y CONFIG_MICROPY_PY_USE_REQUESTS=y CONFIG_MICROPY_PY_USE_ULAB=y diff --git a/micropython/mpy-cross/Makefile b/micropython/mpy-cross/Makefile index 4ff96fc..dac1e8f 100644 --- a/micropython/mpy-cross/Makefile +++ b/micropython/mpy-cross/Makefile @@ -35,7 +35,7 @@ INC += -I$(TOP) # compiler settings CWARN = -Wall -Werror -CWARN += -Wpointer-arith -Wuninitialized +CWARN += -Wpointer-arith -Wuninitialized -Wno-error=return-local-addr CFLAGS = $(INC) $(CWARN) -std=gnu99 $(CFLAGS_MOD) $(COPT) $(CFLAGS_EXTRA) CFLAGS += -fdata-sections -ffunction-sections -fno-asynchronous-unwind-tables