Referring to the Comportable guideline for peripheral device functionality, the module pattgen has the following hardware interfaces defined
- Primary Clock:
clk_i - Other Clocks: none
- Bus Device Interfaces (TL-UL):
tl - Bus Host Interfaces (TL-UL): none
| Pin name | Direction | Description |
|---|---|---|
| pda0_tx | output | Serial output data bit for pattern generation on Channel 0 |
| pcl0_tx | output | Clock corresponding to pattern data on Channel 0 |
| pda1_tx | output | Serial output data bit for pattern generation on Channel 1 |
| pcl1_tx | output | Clock corresponding to pattern data on Channel 1 |
| Port Name | Package::Struct | Type | Act | Width | Description |
|---|---|---|---|---|---|
| tl | tlul_pkg::tl | req_rsp | rsp | 1 |
| Interrupt Name | Type | Description |
|---|---|---|
| done_ch0 | Event | raise if pattern generation on Channel 0 is complete |
| done_ch1 | Event | raise if pattern generation on Channel 1 is complete |
| Alert Name | Description |
|---|---|
| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
| Countermeasure ID | Description |
|---|---|
| PATTGEN.BUS.INTEGRITY | End-to-end bus integrity scheme. |