[gatesim] initial compile clean

Initial check in after compile.

Signed-off-by: Jaedon Kim <[email protected]>

Author: jdonjdon

hw/dv/sv/sec_cm/sec_cm_prim_onehot_check_bind.sv

@@ -3,11 +3,13 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module sec_cm_prim_onehot_check_bind ();
+`ifndef GATE_LEVEL
   bind prim_onehot_check prim_onehot_check_if #(
     .AddrWidth  (AddrWidth),
     .OneHotWidth(OneHotWidth),
     .AddrCheck  (AddrCheck),
     .EnableCheck(EnableCheck),
     .StrictCheck(StrictCheck)
   ) u_prim_onehot_check_if (.*);
+`endif
 endmodule

hw/dv/sv/sec_cm/sec_cm_prim_sparse_fsm_flop_bind.sv

@@ -3,8 +3,10 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module sec_cm_prim_sparse_fsm_flop_bind ();
+`ifndef GATE_LEVEL
   bind prim_sparse_fsm_flop prim_sparse_fsm_flop_if #(
     .Width(Width),
     .CustomForceName(CustomForceName)
   ) u_prim_sparse_fsm_flop_if (.*);
+`endif
 endmodule

hw/ip/clkmgr/dv/sva/clkmgr_bind.sv

@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module clkmgr_bind;
-
+`ifndef GATE_LEVEL
   bind clkmgr tlul_assert #(
     .EndpointType("Device")
   ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o));
@@ -369,4 +369,5 @@ module clkmgr_bind;
     .step_down_acks_sync(u_clkmgr_byp.step_down_acks_sync),
     .extclk_ctrl_sel
   );
+`endif
 endmodule : clkmgr_bind

hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv

@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module pwrmgr_bind;
-
+`ifndef GATE_LEVEL
   bind pwrmgr tlul_assert #(
     .EndpointType("Device")
   ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o));
@@ -81,4 +81,5 @@ module pwrmgr_bind;
     .rom_ctrl_done_i(u_fsm.rom_ctrl_done_i),
     .rom_ctrl_good_i(u_fsm.rom_ctrl_good_i)
   );
+`endif
 endmodule

hw/ip/rstmgr/dv/sva/rstmgr_bind.sv

@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module rstmgr_bind;
-
+`ifndef GATE_LEVEL
   bind rstmgr tlul_assert #(
     .EndpointType("Device")
   ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o));
@@ -69,5 +69,5 @@ module rstmgr_bind;
       resets_o.rst_spi_device_n[1]
     })
   );
-
+`endif
 endmodule

hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv

@@ -119,6 +119,7 @@ initial begin
     force tb.dut.top_earlgrey.u_xbar_main.rst_spi_host1_ni = rst_n;
     force tb.dut.top_earlgrey.u_xbar_peri.rst_peri_ni = rst_n;
 
+`ifndef GATE_LEVEL
     `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__corei, rv_core_ibex, corei_tl_h)
     `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__cored, rv_core_ibex, cored_tl_h)
     `DRIVE_CHIP_TL_HOST_IF(rv_dm__sba, rv_dm, sba_tl_h)
@@ -172,7 +173,7 @@ initial begin
     `DRIVE_CHIP_TL_DEVICE_IF(sysrst_ctrl_aon, sysrst_ctrl_aon, tl)
     `DRIVE_CHIP_TL_DEVICE_IF(adc_ctrl_aon, adc_ctrl_aon, tl)
     `DRIVE_CHIP_TL_EXT_DEVICE_IF(ast, ast, tl)
-
+`endif
 
     // And this can consume time, so they go at the end of this block.
 

hw/top_earlgrey/dv/chip_sim.core

@@ -7,10 +7,13 @@ description: "Earlgrey chip DV sim target"
 filesets:
   files_rtl:
     depend:
-      - lowrisc:systems:top_earlgrey
+      - "!gatelevel ? (lowrisc:systems:top_earlgrey)"
       - lowrisc:systems:top_earlgrey_pkg
-      - lowrisc:systems:chip_earlgrey_asic
+      - "!gatelevel ? (lowrisc:systems:chip_earlgrey_asic)"
       - lowrisc:ibex:ibex_tracer
+    files:
+      - "gatelevel ? (../../../../mapped.v)"
+    file_type: systemVerilogSource
 
   files_dv:
     depend:

hw/top_earlgrey/dv/env/ast_supply_if.sv

@@ -48,18 +48,22 @@ interface ast_supply_if (
 
   // Wait some clock cycles due to various flops in the logic.
   task automatic reenable_vcmain_assertion();
+`ifndef GATE_LEVEL
     repeat (CyclesBeforeReenablingAssert) @(posedge clk);
     `uvm_info("ast_supply_if", "re-enabling vcmain_supp_i related SVA", UVM_MEDIUM)
     $asserton(1, top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A);
+`endif
   endtask
 
   task static force_vcmain_pok(bit value);
+`ifndef GATE_LEVEL
     `uvm_info("ast_supply_if", $sformatf("forcing vcmain_pok_h_o to %b", value), UVM_MEDIUM)
     if (!value) begin
       `uvm_info("ast_supply_if", "disabling vcmain_supp_i related SVA", UVM_MEDIUM)
       $assertoff(1, top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A);
     end
     force u_ast.u_rglts_pdm_3p3v.vcmain_pok_h_o = value;
+`endif
   endtask
 
 `define GLITCH_VCMAIN_POK                 \