doc(uart): correct 'water mark' to 'watermark'

Signed-off-by: RAGUL D <[email protected]>

Author: d-ragul

hw/ip/uart/doc/theory_of_operation.md

@@ -10,8 +10,7 @@
 
 The TX/RX serial lines are high when idle. Data starts with a START bit (high
 idle state deasserts, **1**-->**0**) followed by 8 data bits. The least
-significant bit is sent first. If the parity feature is turned on then an odd or
-even parity bit follows after the data bits. Finally a STOP (**1**) bit
+significant bit is sent first. If the parity feature is turned on then an odd oreven parity bit follows after the data bits. Finally a STOP (**1**) bit
 completes one byte of data transfer.
 
 ```wavejson
@@ -54,7 +53,7 @@ If TX is not enabled, written DATA into FIFO will be stacked up and sent out
 when TX is enabled.
 
 When the FIFO becomes empty as part of transmission, a TX FIFO done interrupt will be raised when the final byte has finished transmitting.
-This is separate from the TX FIFO water mark interrupt.
+This is separate from the TX FIFO watermark interrupt.
 
 
 ### Reception
@@ -166,9 +165,9 @@ UART module has a few interrupts including general data flow interrupts
 and unexpected event interrupts.
 
 #### tx_watermark / tx_empty / rx_watermark
-If the TX FIFO level becomes smaller than the TX water mark level (configurable via [`FIFO_CTRL.TXILVL`](registers.md#fifo_ctrl--txilvl)), the `tx_watermark` interrupt is raised to inform SW.
+If the TX FIFO level becomes smaller than the TX watermark level (configurable via [`FIFO_CTRL.TXILVL`](registers.md#fifo_ctrl--txilvl)), the `tx_watermark` interrupt is raised to inform SW.
 If the TX FIFO is empty, the `tx_empty` interrupt is raised to inform SW.
-If the RX FIFO level becomes greater than or equal to RX water mark level (configurable via [`FIFO_CTRL.RXILVL`](registers.md#fifo_ctrl--rxilvl)), the `rx_watermark` interrupt is raised to inform SW.
+If the RX FIFO level becomes greater than or equal to RX watermark level (configurable via [`FIFO_CTRL.RXILVL`](registers.md#fifo_ctrl--rxilvl)), the `rx_watermark` interrupt is raised to inform SW.
 
 Note that the watermark interrupts and the empty interrupt are level-based status interrupts.
 They will stay asserted for as long as the FIFO levels are in violation of the configured level and cannot be cleared by writing to the status register.