[bazel] Rework HW files targets

This commit switches the HW targets (verilator, bitstream) to use
the target create by `opentitan_top`. This allows to remove many of
the hacky `all_files` targets used everywhere. This commit does keep
a few and even creates some, but tries to adhere to the following
convention: only use `glob()` or `all_files` for sub-directories
that contain no bazel targets and should be passed "as-is" to
fusesoc.

Signed-off-by: Amaury Pouly <[email protected]>

Author: pamaury

BUILD.bazel

@@ -14,8 +14,10 @@ filegroup(
     name = "cores",
     srcs = [
         "check_tool_requirements.core",
+        "tool_requirements.py",
         "topgen.core",
         "topgen-reg-only.core",
+        "//util:check_tool_requirements.py",
     ],
 )
 

hw/BUILD

@@ -35,7 +35,7 @@ string_list_flag(
 fusesoc_build(
     name = "verilator_real",
     srcs = [
-        ":all_files",
+        "//hw/top",
     ],
     cores = [
         "//:cores",
@@ -101,25 +101,6 @@ genrule(
     visibility = ["//visibility:public"],
 )
 
-# TODO(lowRISC/opentitan#7972): Globbing all of the //hw/... hierarchy together
-# is a bit of a hack.  Longer term, we need proper rules for expressing the
-# relationships between verilog components.
-filegroup(
-    name = "all_files",
-    srcs = glob(
-        ["**"],
-        # TODO(lowRISC/opentitan#15882): make Verilator work with foundry repo present.
-        exclude = ["foundry/**"],
-    ) + [
-        "//:tool_requirements.py",
-        "//hw/ip:all_files",
-        "//hw/ip_templates:all_files",
-        "//hw/top_earlgrey:all_files",
-        "//util:check_tool_requirements.py",
-    ],
-    visibility = ["//visibility:public"],
-)
-
 pkg_files(
     name = "package",
     srcs = ["verilator_bin"],

hw/bitstream/vivado/BUILD

@@ -40,7 +40,7 @@ fusesoc_build(
     name = "fpga_cw310",
     testonly = True,
     srcs = [
-        "//hw:all_files",
+        "//hw/top",
         _CW310_TESTROM,
         _OTP_RMA,
     ],
@@ -90,7 +90,7 @@ fusesoc_build(
     name = "fpga_cw310_hyperdebug",
     testonly = True,
     srcs = [
-        "//hw:all_files",
+        "//hw/top",
         _CW310_TESTROM,
         _OTP_RMA,
     ],
@@ -140,7 +140,7 @@ fusesoc_build(
     name = "fpga_cw340",
     testonly = True,
     srcs = [
-        "//hw:all_files",
+        "//hw/top",
         _CW340_TESTROM,
         _OTP_RMA,
     ],

hw/ip/tlul/data/BUILD renamed to hw/dv/BUILD

@@ -6,5 +6,7 @@ package(default_visibility = ["//visibility:public"])
 
 filegroup(
     name = "all_files",
-    srcs = glob(["**"]),
+    srcs = glob(
+        ["**"],
+    ),
 )

hw/ip/BUILD

@@ -3,42 +3,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
 package(default_visibility = ["//visibility:public"])
-
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-        "//hw/ip/adc_ctrl",
-        "//hw/ip/aes",
-        "//hw/ip/aon_timer",
-        "//hw/ip/csrng",
-        "//hw/ip/edn",
-        "//hw/ip/entropy_src",
-        "//hw/ip/gpio",
-        "//hw/ip/hmac",
-        "//hw/ip/i2c",
-        "//hw/ip/keymgr",
-        "//hw/ip/kmac",
-        "//hw/ip/lc_ctrl",
-        "//hw/ip/otbn:all_files",
-        "//hw/ip/otp_ctrl",
-        "//hw/ip/pattgen",
-        "//hw/ip/pinmux:all_files",
-        "//hw/ip/prim",
-        "//hw/ip/prim_generic:all_files",
-        "//hw/ip/prim_xilinx:all_files",
-        "//hw/ip/prim_xilinx_ultrascale:all_files",
-        "//hw/ip/pwm",
-        "//hw/ip/rom_ctrl",
-        "//hw/ip/rv_core_ibex",
-        "//hw/ip/rv_dm",
-        "//hw/ip/rv_timer",
-        "//hw/ip/spi_device",
-        "//hw/ip/spi_host",
-        "//hw/ip/sram_ctrl",
-        "//hw/ip/sysrst_ctrl",
-        "//hw/ip/tlul",
-        "//hw/ip/trial1:all_files",
-        "//hw/ip/uart",
-        "//hw/ip/usbdev",
-    ],
-)

hw/ip/prim/BUILD

@@ -6,12 +6,6 @@ load("//rules/opentitan:hw.bzl", "opentitan_ip")
 
 package(default_visibility = ["//visibility:public"])
 
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-    ],
-)
-
 opentitan_ip(
     name = "prim",
     doc = glob(["doc/**"]),

hw/ip/tlul/BUILD

@@ -6,13 +6,6 @@ load("//rules/opentitan:hw.bzl", "opentitan_ip")
 
 package(default_visibility = ["//visibility:public"])
 
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-        "//hw/ip/tlul/data:all_files",
-    ],
-)
-
 opentitan_ip(
     name = "tlul",
     doc = glob(["doc/**"]),

hw/ip_templates/BUILD

@@ -3,13 +3,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
 package(default_visibility = ["//visibility:public"])
-
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-        "//hw/ip_templates/clkmgr:all_files",
-        "//hw/ip_templates/flash_ctrl:all_files",
-        "//hw/ip_templates/pwrmgr:all_files",
-        "//hw/ip_templates/rstmgr:all_files",
-    ],
-)

hw/ip_templates/pwrmgr/BUILD

@@ -6,5 +6,7 @@ package(default_visibility = ["//visibility:public"])
 
 filegroup(
     name = "all_files",
-    srcs = glob(["**"]),
+    srcs = glob(
+        ["**"],
+    ),
 )

hw/ip_templates/rstmgr/BUILD

@@ -70,19 +70,19 @@ opentitan_top(
     ],
     rtl = glob([
         "*.core",
-        "dv/**",
         "rtl/**",
         "lint/**",
-    ]),
-)
-
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
+        "util/**",
+    ]) + [
+        "//:cores",  # FIXME move those files somewhere else?
+        "//hw/dv:all_files",
+        "//hw/lint:all_files",
+        "//hw/top_earlgrey/dv:all_files",
+        "//hw/vendor:all_files",
+        # The following will be moved to a proper IP when the pinmux port to ipgen is complete.
+        "//hw/ip/pinmux:all_files",
         "//hw/top_earlgrey/data:all_files",
-        "//hw/top_earlgrey/dv/verilator:all_files",
-        "//hw/top_earlgrey/ip:all_files",
-        "//hw/top_earlgrey/sw:all_files",
+        "//hw/top_earlgrey/ip/pinmux:all_files",
     ],
 )
 

hw/ip_templates/clkmgr/BUILD renamed to hw/lint/BUILD

@@ -4,6 +4,11 @@
 
 package(default_visibility = ["//visibility:public"])
 
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)
+
 filegroup(
     name = "config",
     srcs = [

hw/top_earlgrey/BUILD

@@ -6,12 +6,6 @@ load("//rules/opentitan:hw.bzl", "opentitan_ip")
 
 package(default_visibility = ["//visibility:public"])
 
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-    ],
-)
-
 opentitan_ip(
     name = "xbar",
     doc = glob(["doc/**"]),

hw/top_earlgrey/dv/BUILD

@@ -6,13 +6,6 @@ load("//rules/opentitan:hw.bzl", "opentitan_ip")
 
 package(default_visibility = ["//visibility:public"])
 
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-        "//hw/top_earlgrey/ip/xbar_main/data:all_files",
-    ],
-)
-
 opentitan_ip(
     name = "xbar_main",
     doc = glob(["doc/**"]),

hw/top_earlgrey/dv/verilator/BUILD

@@ -6,13 +6,6 @@ load("//rules/opentitan:hw.bzl", "opentitan_ip")
 
 package(default_visibility = ["//visibility:public"])
 
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]) + [
-        "//hw/top_earlgrey/ip/xbar_peri/data:all_files",
-    ],
-)
-
 opentitan_ip(
     name = "xbar_peri",
     doc = glob(["doc/**"]),

hw/top_earlgrey/ip/BUILD

@@ -21,8 +21,3 @@ ld_library(
     name = "top_earlgrey_memory",
     includes = ["top_earlgrey_memory.ld"],
 )
-
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]),
-)

hw/top_earlgrey/ip/xbar/BUILD

@@ -6,13 +6,8 @@ load("@rules_rust//rust:defs.bzl", "rust_library")
 
 package(default_visibility = ["//visibility:public"])
 
-filegroup(
-    name = "all_files",
-    srcs = glob(["**"]),
-)
-
 rust_library(
     name = "top_earlgrey",
-    srcs = [":all_files"],
+    srcs = glob(["*.rs"]),
     crate_root = "mod.rs",
 )

hw/top_earlgrey/ip/xbar_main/BUILD

@@ -6,5 +6,7 @@ package(default_visibility = ["//visibility:public"])
 
 filegroup(
     name = "all_files",
-    srcs = glob(["**"]),
+    srcs = glob(
+        ["**"],
+    ),
 )