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[flash_ctrl/fi] Add VC-Z01X FI analysis support to flash_ctrl
This commit adds the FI sim configuration files needed to run VC-Z01X on the flash controller. Signed-off-by: Pascal Nasahl <[email protected]>
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hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson

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name: xcelium_crypto_dpi_prince_build_opts
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build_opts: ["-I{build_dir}/fusesoc-work/src/{crypto_prince_ref_src_dir}"]
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}
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{
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name: z01x_crypto_dpi_prince_build_opts
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build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{crypto_prince_ref_src_dir}"]
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}
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]
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}
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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FaultGenerate {
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NA [0,1] {PORT "tb.dut.u_eflash.gen_flash_cores[0].**"}
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}
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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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module strobe;
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// Enable TL-UL integrity checker strobing points.
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`define FI_SIM_Z01X
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initial begin
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@(posedge tb.dut.rst_ni)
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// Start FI injection job. For permanent faults, faults are injected
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// at this point. For transient faults, the cycle counter starts from
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// here.
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$fs_inject;
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end
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integer cmp;
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// Compare outputs of the golden and faulty machine. If we detect a mismatch,
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// set the fault status to "observed, not detected" (ON). If the faulty machine
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// produced an invalid value (X/Z), set to "potentially observed, not detected"
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// (PN).
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always@(negedge tb.dut.clk_i) begin
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cmp = $fs_compare(tb.dut.mem_tl_o, tb.dut.prim_tl_o, tb.dut.core_tl_o);
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if (1 == cmp) begin
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// Mismatch beetween the golden and faulty machine.
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$fs_set_status("ON", "tb.dut.mem_tl_o, tb.dut.prim_tl_o, tb.dut.core_tl_o");
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end else if (2 == cmp) begin
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// Faulty machine has a X/Z at the output.
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$fs_set_status("PN", "tb.dut.mem_tl_o, tb.dut.prim_tl_o, tb.dut.core_tl_o");
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end
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end
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// In the previous always block, we have classified the fault as ON or PN. Now
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// check, if one of the countermeasures has detected the fault. Then, set the
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// fault status to "observed detected" (OD) or "potentially observed, detected"
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// (PD). If one of the alert signal is invalid (X/Z), set to "observed, potentially
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// detected" (OP), "potentially observed, potentially detected" (PP), or "not
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// detected, potentially observed" (NP).
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string status;
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always@(negedge tb.dut.clk_i) begin
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#2;
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cmp = $fs_compare(tb.dut.alert_srcs, tb.dut.mem_tl_intg_err, tb.dut.prim_tl_intg_err,
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tb.dut.core_tl_intg_err, tb.dut.flash_host_rderr);
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status = $fs_get_status();
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if (1 == cmp) begin
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if (status == "ON") begin
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// Mismatch between golden and faulty machine and the alert was triggered.
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$fs_drop_status("OD", {"tb.dut.alert_srcs, tb.dut.mem_tl_intg_err,",
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"tb.dut.prim_tl_intg_err, tb.dut.core_tl_intg_err,",
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"tb.dut.flash_host_rderr"});
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end else if (status == "PN") begin
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// Potential mismatch between golden and faulty machine and the alert was triggered.
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$fs_drop_status("PD", {"tb.dut.alert_srcs, tb.dut.mem_tl_intg_err,",
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"tb.dut.prim_tl_intg_err, tb.dut.core_tl_intg_err,",
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"tb.dut.flash_host_rderr"});
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end else begin
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// No mismatch between golden and faulty machine but the alert was triggered.
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$fs_set_status("ND", {"tb.dut.alert_srcs, tb.dut.mem_tl_intg_err,",
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"tb.dut.prim_tl_intg_err, tb.dut.core_tl_intg_err,",
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"tb.dut.flash_host_rderr"});
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end
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end else if (2 == cmp) begin
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if (status == "ON") begin
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// Mismatch between golden and faulty machine and the alert was potentially triggered.
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$fs_drop_status("OP", {"tb.dut.alert_srcs, tb.dut.mem_tl_intg_err,",
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"tb.dut.prim_tl_intg_err, tb.dut.core_tl_intg_err,",
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"tb.dut.flash_host_rderr"});
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end else if (status == "PN") begin
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// Potential mismatch between golden and faulty machine and the alert was potentially
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// triggered.
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$fs_drop_status("PP", {"tb.dut.alert_srcs, tb.dut.mem_tl_intg_err,",
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"tb.dut.prim_tl_intg_err, tb.dut.core_tl_intg_err,",
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"tb.dut.flash_host_rderr"});
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end else begin
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// No mismatch between golden and faulty machine but the alert was potentially triggered.
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$fs_set_status("NP", {"tb.dut.alert_srcs, tb.dut.mem_tl_intg_err,",
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"tb.dut.prim_tl_intg_err, tb.dut.core_tl_intg_err,",
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"tb.dut.flash_host_rderr"});
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end
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end
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end
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endmodule

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