Reduce CW340 bootstrap SPI clock speed

engdoreis · engdoreis · commit 9ed5182d2c07 · 2025-11-21T11:41:00.000Z
The reduction is necessary due to increased bus capacitance introduced by external wires connected
to the TPM SPI interface, which affects signal integrity.
This change improves CW340 stability during bootstrap for CI tests.

Signed-off-by: Douglas Reis &lt;doreis@lowrisc.org&gt;
diff --git a/sw/host/opentitanlib/src/app/config/hyperdebug_cw340.json b/sw/host/opentitanlib/src/app/config/hyperdebug_cw340.json
@@ -88,7 +88,7 @@
   "spi": [
     {
       "name": "BOOTSTRAP",
-      "bits_per_sec": 5000000,
+      "bits_per_sec": 4000000,
       "chip_select": "CN10_6",
       "alias_of": "QSPI"
     }

Original file line number	Diff line number	Diff line change
`@@ -88,7 +88,7 @@`
`88`	`88`	`"spi": [`
`89`	`89`	`{`
`90`	`90`	`"name": "BOOTSTRAP",`
`91`		`- "bits_per_sec": 5000000,`
	`91`	`+ "bits_per_sec": 4000000,`
`92`	`92`	`"chip_select": "CN10_6",`
`93`	`93`	`"alias_of": "QSPI"`
`94`	`94`	`}`