diff --git a/hw/ip/rv_dm/data/rv_dm.hjson b/hw/ip/rv_dm/data/rv_dm.hjson index 3a7fbd6c93267..c54db704813f7 100644 --- a/hw/ip/rv_dm/data/rv_dm.hjson +++ b/hw/ip/rv_dm/data/rv_dm.hjson @@ -30,6 +30,7 @@ { protocol: "tlul", direction: "host", name: "sba" } { protocol: "tlul", direction: "device", name: "regs" } { protocol: "tlul", direction: "device", name: "mem" } + { protocol: "tlul", direction: "device", name: "dbg" } ], scan: "true", // Enable `scanmode_i` port scan_reset: "true", // Enable `scan_rst_ni` port @@ -108,26 +109,6 @@ asserted when the hardware debug mechanisms are enabled in the system. ''' }, - { - struct: "tl_h2d" - package: "tlul_pkg" - type: "uni" - name: "dmi_tl_h2d" - act: "rcv" - desc: ''' - TLUL-based DMI request input port - ''' - } - { - struct: "tl_d2h" - package: "tlul_pkg" - type: "uni" - name: "dmi_tl_d2h" - act: "req" - desc: ''' - TLUL-based DMI response output port - ''' - } { struct: "lc_tx" type: "uni" name: "lc_dft_en" @@ -658,5 +639,18 @@ } }, ] + // Debug bus attachment + dbg: [ + { window: { + name: "dbg" + // 0x0 ... 0x40 word addresses are allocated here. + items: "128" + swaccess: "rw", + data-intg-passthru: "true", + byte-write: "false", + desc: '''Access window to DM CSRs.''' + } + }, + ] } } diff --git a/hw/ip/rv_dm/doc/interfaces.md b/hw/ip/rv_dm/doc/interfaces.md index a42ed953815ed..97eead563629c 100644 --- a/hw/ip/rv_dm/doc/interfaces.md +++ b/hw/ip/rv_dm/doc/interfaces.md @@ -8,7 +8,7 @@ All hardware interfaces of the debug system are documented in the [PULP RISC-V D Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`rv_dm`** has the following hardware interfaces defined - Primary Clock: **`clk_i`** - Other Clocks: **`clk_lc_i`** -- Bus Device Interfaces (TL-UL): **`regs_tl_d`**, **`mem_tl_d`** +- Bus Device Interfaces (TL-UL): **`regs_tl_d`**, **`mem_tl_d`**, **`dbg_tl_d`** - Bus Host Interfaces (TL-UL): **`sba_tl_h`** - Peripheral Pins for Chip IO: *none* - Interrupts: *none* @@ -20,8 +20,6 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | next_dm_addr | rv_dm_pkg::next_dm_addr | uni | rcv | 1 | 32bit word address of the next debug module. Set to 0x0 if this is the last debug module in the chain. | | jtag | jtag_pkg::jtag | req_rsp | rsp | 1 | JTAG signals for the RISC-V TAP. | | lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the hardware debug mechanisms are enabled in the system. | -| dmi_tl_h2d | tlul_pkg::tl_h2d | uni | rcv | 1 | TLUL-based DMI request input port | -| dmi_tl_d2h | tlul_pkg::tl_d2h | uni | req | 1 | TLUL-based DMI response output port | | lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the DFT mechanisms are enabled in the system. | | pinmux_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Multibit life cycle hardware debug enable signal coming from pinmux. This is a latched version of the lc_hw_debug_en signal and is only used to gate the JTAG / TAP side of the RV_DM. It is used to keep a debug session live while the rest of the system undergoes an NDM reset. | | otp_dis_rv_dm_late_debug | prim_mubi_pkg::mubi8 | uni | rcv | 1 | | @@ -36,6 +34,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | sba_tl_h | tlul_pkg::tl | req_rsp | req | 1 | | | regs_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | | mem_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | +| dbg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts diff --git a/hw/ip/rv_dm/doc/registers.md b/hw/ip/rv_dm/doc/registers.md index a5caadcd4075d..7be081cea1e13 100644 --- a/hw/ip/rv_dm/doc/registers.md +++ b/hw/ip/rv_dm/doc/registers.md @@ -863,5 +863,19 @@ Access window into the debug ROM. - Access: `ro` - Byte writes are *not* supported. +## Summary of the **`dbg`** interface's registers + +| Name | Offset | Length | Description | +|:--------------------|:---------|---------:|:--------------------------| +| rv_dm.[`dbg`](#dbg) | 0x0 | 512 | Access window to DM CSRs. | + +## dbg +Access window to DM CSRs. + +- Word Aligned Offset Range: `0x0`to`0x1fc` +- Size (words): `128` +- Access: `rw` +- Byte writes are *not* supported. + diff --git a/hw/ip/rv_dm/dv/sva/rv_dm_bind.sv b/hw/ip/rv_dm/dv/sva/rv_dm_bind.sv index 3537674f1dfb4..e128dcdb55b42 100644 --- a/hw/ip/rv_dm/dv/sva/rv_dm_bind.sv +++ b/hw/ip/rv_dm/dv/sva/rv_dm_bind.sv @@ -9,8 +9,8 @@ module rv_dm_bind; ) tlul_assert_device_dmi ( .clk_i, .rst_ni, - .h2d (dmi_tl_h2d_i), - .d2h (dmi_tl_d2h_o) + .h2d (dbg_tl_d_i), + .d2h (dbg_tl_d_o) ); bind rv_dm tlul_assert #( diff --git a/hw/ip/rv_dm/dv/tb.sv b/hw/ip/rv_dm/dv/tb.sv index c6cea524df389..a94e62d536565 100644 --- a/hw/ip/rv_dm/dv/tb.sv +++ b/hw/ip/rv_dm/dv/tb.sv @@ -26,8 +26,8 @@ module tb; rv_dm_if rv_dm_if(.clk(clk), .rst_n(rst_n)); // Used for JTAG DTM connections via TL-UL. - tlul_pkg::tl_h2d_t dmi_tl_h2d; - tlul_pkg::tl_d2h_t dmi_tl_d2h; + tlul_pkg::tl_h2d_t dbg_tl_h2d; + tlul_pkg::tl_d2h_t dbg_tl_d2h; `DV_ALERT_IF_CONNECT() @@ -43,11 +43,11 @@ module tb; .jtag_o ({jtag_if.tdo, jtag_tdo_oe}), .scan_rst_ni (rv_dm_if.scan_rst_n), .scanmode_i (rv_dm_if.scanmode), - .tl_h2d_o (dmi_tl_h2d), - .tl_d2h_i (dmi_tl_d2h) + .tl_h2d_o (dbg_tl_h2d), + .tl_d2h_i (dbg_tl_d2h) ); `else - assign dmi_tl_h2d = tlul_pkg::TL_H2D_DEFAULT; + assign dbg_tl_h2d = tlul_pkg::TL_H2D_DEFAULT; `endif // dut @@ -100,8 +100,8 @@ module tb; .jtag_o ({jtag_if.tdo, jtag_tdo_oe}), `endif - .dmi_tl_h2d_i (dmi_tl_h2d), - .dmi_tl_d2h_o (dmi_tl_d2h) + .dbg_tl_d_i (dbg_tl_h2d), + .dbg_tl_d_o (dbg_tl_d2h) ); // Apply the muxing that we get in rv_dm, where the JTAG interface that actually connects to the diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv index a5c9dfda61b49..df73f4b52a9fa 100644 --- a/hw/ip/rv_dm/rtl/rv_dm.sv +++ b/hw/ip/rv_dm/rtl/rv_dm.sv @@ -71,8 +71,8 @@ module rv_dm input jtag_pkg::jtag_req_t jtag_i, output jtag_pkg::jtag_rsp_t jtag_o, // TL-UL-based DMI - input tlul_pkg::tl_h2d_t dmi_tl_h2d_i, - output tlul_pkg::tl_d2h_t dmi_tl_d2h_o + input tlul_pkg::tl_h2d_t dbg_tl_d_i, + output tlul_pkg::tl_d2h_t dbg_tl_d_o ); /////////////////////////// @@ -114,7 +114,7 @@ module rv_dm tlul_pkg::tl_h2d_t mem_tl_win_h2d; tlul_pkg::tl_d2h_t mem_tl_win_d2h; rv_dm_reg_pkg::rv_dm_regs_reg2hw_t regs_reg2hw; - logic regs_intg_error, rom_intg_error, dmi_intg_error; + logic regs_intg_error, rom_intg_error, dmi_intg_error, dbg_intg_error; logic sba_gate_intg_error, rom_gate_intg_error, dmi_gate_intg_error; rv_dm_regs_reg_top u_reg_regs ( @@ -135,7 +135,7 @@ module rv_dm // Alerts logic [NumAlerts-1:0] alert_test, alerts; - assign alerts[0] = regs_intg_error | rom_intg_error | dmi_intg_error | + assign alerts[0] = regs_intg_error | rom_intg_error | dmi_intg_error | dbg_intg_error | sba_gate_intg_error | rom_gate_intg_error | dmi_gate_intg_error; assign alert_test = { @@ -436,6 +436,19 @@ module rv_dm // If DMIDirectTAP is defined, a bound-in DPI module replaces the TAP that's defined // within the ifndef block `ifndef DMIDirectTAP + tlul_pkg::tl_h2d_t dbg_tl_h2d_win; + tlul_pkg::tl_d2h_t dbg_tl_d2h_win; + + rv_dm_dbg_reg_top u_rv_dm_dbg_reg_top ( + .clk_i, + .rst_ni, + .tl_i (dbg_tl_d_i), + .tl_o (dbg_tl_d_o), + .tl_win_o (dbg_tl_h2d_win), + .tl_win_i (dbg_tl_d2h_win), + .intg_err_o(dbg_intg_error) + ); + rv_dm_dmi_gate #( .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) ) u_rv_dm_dmi_gate ( @@ -446,14 +459,14 @@ module rv_dm .lc_hw_debug_en_i, .lc_check_byp_en_i, .lc_escalate_en_i, - .dbg_tl_h2d_win_i ( dmi_tl_h2d_i ), - .dbg_tl_d2h_win_o ( dmi_tl_d2h_o ), - .dmi_req_valid_o ( dmi_req_valid ), - .dmi_req_ready_i ( dmi_req_ready ), - .dmi_req_o ( dmi_req ), - .dmi_rsp_valid_i ( dmi_rsp_valid ), - .dmi_rsp_ready_o ( dmi_rsp_ready ), - .dmi_rsp_i ( dmi_rsp ), + .dbg_tl_h2d_win_i ( dbg_tl_h2d_win ), + .dbg_tl_d2h_win_o ( dbg_tl_d2h_win ), + .dmi_req_valid_o ( dmi_req_valid ), + .dmi_req_ready_i ( dmi_req_ready ), + .dmi_req_o ( dmi_req ), + .dmi_rsp_valid_i ( dmi_rsp_valid ), + .dmi_rsp_ready_o ( dmi_rsp_ready ), + .dmi_rsp_i ( dmi_rsp ), // Integrity error .intg_error_o( dmi_intg_error) @@ -559,11 +572,12 @@ module rv_dm `endif // Tied-off and ignore signals from the DMI interface assign dmi_intg_error = 1'b0; + assign dbg_intg_error = 1'b0; assign dmi_gate_intg_error = 1'b0; - assign dmi_tl_d2h_o = tlul_pkg::TL_D2H_DEFAULT; + assign dbg_tl_d_o = tlul_pkg::TL_D2H_DEFAULT; logic unused_signals; - assign unused_signals = ^{dmi_tl_h2d_i, + assign unused_signals = ^{dbg_tl_d_i, lc_check_byp_en_i, lc_escalate_en_i, strap_en_i, @@ -686,8 +700,8 @@ module rv_dm `ASSERT_KNOWN(TlSbaAValidKnown_A, sba_tl_h_o.a_valid) `ASSERT_KNOWN(TlSbaDReadyKnown_A, sba_tl_h_o.d_ready) - `ASSERT_KNOWN(TlDmiDValidKnown_A, dmi_tl_d2h_o.d_valid) - `ASSERT_KNOWN(TlDmiAReadyKnown_A, dmi_tl_d2h_o.a_ready) + `ASSERT_KNOWN(TlDmiDValidKnown_A, dbg_tl_d_o.d_valid) + `ASSERT_KNOWN(TlDmiAReadyKnown_A, dbg_tl_d_o.a_ready) `ASSERT_KNOWN(NdmresetOKnown_A, ndmreset_req_o) `ASSERT_KNOWN(DmactiveOKnown_A, dmactive_o) diff --git a/hw/ip/rv_dm/rtl/rv_dm_dbg_reg_top.sv b/hw/ip/rv_dm/rtl/rv_dm_dbg_reg_top.sv new file mode 100644 index 0000000000000..4d7f13980d4b4 --- /dev/null +++ b/hw/ip/rv_dm/rtl/rv_dm_dbg_reg_top.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rv_dm_dbg_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o, + input tlul_pkg::tl_d2h_t tl_win_i, + + // To HW + + // Integrity check errors + output logic intg_err_o +); + + import rv_dm_reg_pkg::* ; + + + // Add an unloaded flop to make use of clock / reset + // This is done to specifically address lint complaints of unused clocks/resets + // Since the flop is unloaded it will be removed during synthesis + logic unused_reg; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + unused_reg <= '0; + end else begin + unused_reg <= tl_i.a_valid; + end + end + + + + // Since there are no registers in this block, commands are routed through to windows which + // can report their own integrity errors. + assign intg_err_o = 1'b0; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(0) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_win_o = tl_i; + assign tl_o_pre = tl_win_i; + + // Unused signal tieoff +endmodule diff --git a/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv b/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv index e1d61bb9eed6c..f107770839829 100644 --- a/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv +++ b/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv @@ -13,6 +13,7 @@ package rv_dm_reg_pkg; // Address widths within the block parameter int RegsAw = 4; parameter int MemAw = 12; + parameter int DbgAw = 9; /////////////////////////////////////////////// // Typedefs for registers for regs interface // @@ -983,4 +984,9 @@ package rv_dm_reg_pkg; 4'b 1111 // index[280] RV_DM_FLAGS_255 }; + // Window parameters for dbg interface + parameter logic [DbgAw-1:0] RV_DM_DBG_OFFSET = 9'h 0; + parameter int unsigned RV_DM_DBG_SIZE = 'h 200; + parameter int unsigned RV_DM_DBG_IDX = 0; + endpackage diff --git a/hw/ip/rv_dm/rv_dm.core b/hw/ip/rv_dm/rv_dm.core index c22c664a6e964..eed11cb417f86 100644 --- a/hw/ip/rv_dm/rv_dm.core +++ b/hw/ip/rv_dm/rv_dm.core @@ -21,6 +21,7 @@ filesets: files: - rtl/rv_dm_reg_pkg.sv - rtl/rv_dm_regs_reg_top.sv + - rtl/rv_dm_dbg_reg_top.sv - rtl/rv_dm_dmi_gate.sv - rtl/rv_dm_pkg.sv - rtl/rv_dm.sv diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 1ed5cd78145df..ab6543f08f581 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -5707,6 +5707,10 @@ { hart: 0x41200000 } + dbg: + { + hart: 0x00001000 + } } generate_dif: false clock_connections: @@ -5801,28 +5805,6 @@ top_signame: lc_ctrl_lc_hw_debug_en index: -1 } - { - name: dmi_tl_h2d - desc: TLUL-based DMI request input port - struct: tl_h2d - package: tlul_pkg - type: uni - act: rcv - width: 1 - inst_name: rv_dm - index: -1 - } - { - name: dmi_tl_d2h - desc: TLUL-based DMI response output port - struct: tl_d2h - package: tlul_pkg - type: uni - act: req - width: 1 - inst_name: rv_dm - index: -1 - } { name: lc_dft_en desc: @@ -6031,6 +6013,16 @@ top_signame: rv_dm_mem_tl_d index: -1 } + { + name: dbg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + index: -1 + } ] } { @@ -19875,28 +19867,6 @@ top_signame: lc_ctrl_lc_hw_debug_en index: -1 } - { - name: dmi_tl_h2d - desc: TLUL-based DMI request input port - struct: tl_h2d - package: tlul_pkg - type: uni - act: rcv - width: 1 - inst_name: rv_dm - index: -1 - } - { - name: dmi_tl_d2h - desc: TLUL-based DMI response output port - struct: tl_d2h - package: tlul_pkg - type: uni - act: req - width: 1 - inst_name: rv_dm - index: -1 - } { name: lc_dft_en desc: @@ -20105,6 +20075,16 @@ top_signame: rv_dm_mem_tl_d index: -1 } + { + name: dbg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + index: -1 + } { name: irq struct: logic diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index b571fbaa08a04..976784a19c5db 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -757,7 +757,8 @@ // Note that this module also contains a bus host. base_addrs: { mem: {hart: "0x00010000"}, - regs: {hart: "0x41200000"} + regs: {hart: "0x41200000"}, + dbg: {hart: "0x00001000"}, // Not used in Earlgrey }, generate_dif: "False" }, diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index b61147a77b9da..3954683b6b219 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -426,6 +426,7 @@ For the purpose of `top_earlgrey`, the first option has been chosen to benefit s | | | 0x20000000 (mem) | | rv_dm | rv_dm | 0x00010000 (mem) | | | | 0x41200000 (regs) | +| | | 0x00001000 (dbg) | | rv_plic | rv_plic | 0x48000000 (regs) | | aes | aes | 0x41100000 (regs) | | hmac | hmac | 0x41110000 (regs) | diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index bd69eac3fda18..8405c618911e7 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -2203,8 +2203,6 @@ module top_earlgrey #( .jtag_i(pinmux_aon_rv_jtag_req), .jtag_o(pinmux_aon_rv_jtag_rsp), .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), - .dmi_tl_h2d_i(tlul_pkg::TL_H2D_DEFAULT), - .dmi_tl_d2h_o(), .lc_dft_en_i(lc_ctrl_lc_dft_en), .pinmux_hw_debug_en_i(pinmux_aon_pinmux_hw_debug_en), .otp_dis_rv_dm_late_debug_i(rv_dm_otp_dis_rv_dm_late_debug), @@ -2222,6 +2220,8 @@ module top_earlgrey #( .regs_tl_d_o(rv_dm_regs_tl_d_rsp), .mem_tl_d_i(rv_dm_mem_tl_d_req), .mem_tl_d_o(rv_dm_mem_tl_d_rsp), + .dbg_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .dbg_tl_d_o(), .scanmode_i, .scan_rst_ni, diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 74d4088d1c6f5..85d83ea1c6fa8 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -371,6 +371,16 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES = 32'h1000; + /** + * Peripheral base address for dbg device on rv_dm in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RV_DM_DBG_BASE_ADDR = 32'h1000; + + /** + * Peripheral size in bytes for dbg device on rv_dm in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES = 32'h200; + /** * Peripheral base address for rv_plic in top earlgrey. */ diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index 26468a3108951..e74c119a44b80 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -525,6 +525,20 @@ pub const RV_DM_MEM_BASE_ADDR: usize = 0x10000; /// `RV_DM_MEM_BASE_ADDR + RV_DM_MEM_SIZE_BYTES`. pub const RV_DM_MEM_SIZE_BYTES: usize = 0x1000; +/// Peripheral base address for dbg device on rv_dm in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_DM_DBG_BASE_ADDR: usize = 0x1000; + +/// Peripheral size for dbg device on rv_dm in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_DM_DBG_BASE_ADDR and +/// `RV_DM_DBG_BASE_ADDR + RV_DM_DBG_SIZE_BYTES`. +pub const RV_DM_DBG_SIZE_BYTES: usize = 0x200; + /// Peripheral base address for rv_plic in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 1a33c5ff60ee6..e903296bc14df 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -673,6 +673,24 @@ extern "C" { */ #define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000u +/** + * Peripheral base address for dbg device on rv_dm in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000u + +/** + * Peripheral size for dbg device on rv_dm in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and + * `TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200u + /** * Peripheral base address for rv_plic in top earlgrey. * diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index dfb78058d492b..abb977b1beda4 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -675,6 +675,23 @@ * `TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES`. */ #define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000 +/** + * Peripheral base address for dbg device on rv_dm in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000 + +/** + * Peripheral size for dbg device on rv_dm in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and + * `TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200 /** * Peripheral base address for rv_plic in top earlgrey. *