Best Practice for Extracting Earlgrey RTL for ASIC Synthesis/GDSII Flow

[shivarammysore]

Best Practice for Extracting Earlgrey RTL for ASIC Synthesis/GDSII Flow

Context

I'm experimenting with an ASIC synthesis flow for the OpenTitan Earlgrey SoC. I need to extract all RTL files (including typedefs, packages, and dependencies) required for a complete RTL-to-GDSII flow outside of the Bazel build environment.

Current Understanding

Based on the directory structure documentation, I understand that:

1. Source RTL is in hw/ip/*/rtl/ for standard IPs
2. Auto-generated RTL is in:
   • hw/top_earlgrey/rtl/autogen/ (top-level integration)
   • hw/top_earlgrey/ip_autogen/*/rtl/ (generated IPs like clkmgr, rstmgr, etc.)
   • hw/ip/*/rtl/autogen/ (IP-level generated files)
3. Vendor IPs are in hw/vendor/lowrisc_ibex/, etc.
4. Package/typedef files (e.g., *_pkg.sv, top_pkg.sv, prim_util_pkg.sv) define types and constants
5. Build metadata (.hjson, .core files) are not RTL

Questions

1. Complete File List

What is the recommended way to get a complete list of all .sv/.v/.svh files needed for Earlgrey ASIC synthesis?

Options I'm considering:

• a) Parse hw/top_earlgrey/top_earlgrey.core and recursively resolve dependencies
• b) Run Bazel build first, then extract from bazel-bin/ and source tree
• c) Use FuseSoC to generate the file list
• d) Something else?

2. Auto-Generated Files

Do I need to run the OpenTitan build process first to generate all autogen/ files?

bazel build //hw/top_earlgrey:top_earlgrey

Or are there pre-built/committed auto-generated files I can use directly?

3. Package and Typedef Dependencies

How do I ensure all package files (*_pkg.sv) and typedef definitions are included?

I've noticed files like:

• prim_util_pkg.sv, prim_mubi_pkg.sv, prim_subreg_pkg.sv (primitives)
• top_pkg.sv, top_racl_pkg.sv (top-level)
• tlul_pkg.sv (bus protocol)
• Various IP-specific *_pkg.sv files

Are these all located in rtl/ directories, or are some generated elsewhere? What's the best way to ensure all typedef/package dependencies are captured?

4. Synthesis-Ready Subset

For ASIC synthesis (not simulation/verification), which directories should I include/exclude?

My current approach:

INCLUDE:
✅ hw/top_earlgrey/rtl/ (including autogen/)
✅ hw/top_earlgrey/ip/*/rtl/
✅ hw/top_earlgrey/ip_autogen/*/rtl/
✅ hw/ip/*/rtl/ (including *_pkg.sv files)
✅ hw/vendor/lowrisc_ibex/rtl/

EXCLUDE:
❌ hw/*/dv/ (testbenches)
❌ hw/*/data/ (build metadata)
❌ *.hjson, *.core (not synthesizable)
❌ hw/*/doc/ (documentation)

Is this correct, or am I missing something?

5. Dependency Order

Does the order of .sv files matter for synthesis tools?

Should I follow a specific inclusion order (e.g., packages first, then primitives, then IPs, then top-level)?

6. Chip vs. Top

For ASIC flow, should I use:

• hw/top_earlgrey/rtl/autogen/top_earlgrey.sv (SoC core), or
• hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv (with pads/IO)?

What's the difference in terms of what each targets?

My Current Approach

I've written a script that:

1. Copies all rtl/ directories (including autogen/) from:
   • hw/top_earlgrey/
   • hw/ip/ (all IPs)
   • hw/top_earlgrey/ip_autogen/
   • hw/vendor/lowrisc_ibex/
2. Excludes all non-RTL files (.hjson, .core, data/, doc/, dv/)
3. Preserves directory structure for traceability

Is this the right approach? Or is there an official/recommended method?

Use Case Details

• Target: Full Earlgrey SoC ASIC
• Environment: Non-Bazel synthesis flow
• Goal: Complete RTL-to-GDSII flow with external tools

Additional Info

• I have successfully built Earlgrey with Bazel
• I can access bazel-bin/ and build-out/ directories
• I'm familiar with the .core file format (FuseSoC)
• Working on Ubuntu 22.04 with 88-core machine

Expected Outcome

Ideally, I'd like to know:

1. The canonical/recommended way to extract synthesis-ready RTL
2. Whether my current approach is correct or missing critical files
3. Any gotchas or common pitfalls when using OpenTitan RTL outside the Bazel build system

Thank you for any guidance! 🙏