diff --git a/.gitignore b/.gitignore index 994a1ff4917f3..21925476ad991 100644 --- a/.gitignore +++ b/.gitignore @@ -91,3 +91,8 @@ book # Custom Ruff config overrides .ruff.toml + +# Synopsys Z01X configuration files +*.sff +hw/dv/tools/fi_sim.tcl +hw/dv/tools/dvsim/z01x.hjson diff --git a/hw/dv/tools/dvsim/sim.mk b/hw/dv/tools/dvsim/sim.mk index bd03c81d28a58..d673b883c0d88 100644 --- a/hw/dv/tools/dvsim/sim.mk +++ b/hw/dv/tools/dvsim/sim.mk @@ -38,7 +38,7 @@ do_build: gen_sv_flist post_build: do_build @echo "[make]: post_build" ifneq (${post_build_cmds},) - cd ${build_dir} && ${post_build_cmds} + cd ${build_dir} && ${post_build_cmds} ${post_build_opts} endif build_result: post_build @@ -183,7 +183,11 @@ endif simulate: sw_build @echo "[make]: simulate" +ifeq (${SIMULATOR}, z01x) + cd ${run_dir} && ${run_cmd} ${fi_sim_run_opts} +else cd ${run_dir} && ${run_cmd} ${run_opts} +endif post_run: simulate @echo "[make]: post_run" diff --git a/hw/dv/tools/z01x/README.md b/hw/dv/tools/z01x/README.md new file mode 100644 index 0000000000000..63b42baba6e81 --- /dev/null +++ b/hw/dv/tools/z01x/README.md @@ -0,0 +1,21 @@ +# Synopsys VC Z01X Fault Injection Simulation + +This tool, which is integrated into OpenTitan, enables users to conduct a pre-silicon fault injection analysis. +During simulation, Z01X injects faults based on user contraints, and compares the golden vs. the faulty model. + +## Usage + +Z01X proprietary configuration files are available in the [opentitan_fi_z01x](https://github.com/lowRISC/opentitan_fi_z01x) repository. +Please contact [info@lowrisc.org](mailto:info@lowrisc.org?subject=VC-ZOIX%20access) with the email subject: "VC-ZOIX access" to request access to this repository. + +Once you have access, follow these steps: +```bash +$ git clone git@github.com:lowRISC/opentitan_fi_z01x.git +$ git clone git@github.com:lowRISC/opentitan.git +$ export Z01X_DIR= +$ export OT_DIR= +$ cd opentitan/ +$ ./util/prepare_dvsim_z01x.sh +$ ./util/dvsim/dvsim.py hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson \ + -i flash_ctrl_basic_rw -t z01x --reseed-multiplier 0.0001 --fixed-seed 1 +``` diff --git a/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson b/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson index 29a6550735c7a..840591b5ca9b3 100644 --- a/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson +++ b/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson @@ -18,5 +18,10 @@ name: xcelium_crypto_dpi_prince_build_opts build_opts: ["-I{build_dir}/fusesoc-work/src/{crypto_prince_ref_src_dir}"] } + + { + name: z01x_crypto_dpi_prince_build_opts + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{crypto_prince_ref_src_dir}"] + } ] } diff --git a/hw/ip/sram_ctrl/dv/sram_ctrl_base_fi_sim_cfg.hjson b/hw/ip/sram_ctrl/dv/sram_ctrl_base_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..fc898dbc9f06f --- /dev/null +++ b/hw/ip/sram_ctrl/dv/sram_ctrl_base_fi_sim_cfg.hjson @@ -0,0 +1,173 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: sram_ctrl + + // Top level dut name (sv module). + dut: sram_ctrl + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: z01x + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:sram_ctrl_fi_sim:0.1 + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/sram_ctrl/data/sram_ctrl_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{proj_root}/hw/ip/sram_ctrl/data/sram_ctrl.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for prim_ram_1p_scr + "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson" + "{proj_root}/hw/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson" + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson" + ] + + en_build_modes: ["vcs_memutil_dpi_scrambled_build_opts"] + + // Add additional tops for simulation. + sim_tops: ["sram_ctrl_bind", "sram_ctrl_cov_bind", + "sec_cm_prim_onehot_check_bind", "sec_cm_prim_count_bind", + "strobe"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + vcs_cov_excl_files: ["{proj_root}/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el", + "{proj_root}/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el"] + + // Need to override the default output directory + overrides: [ + { + name: scratch_path + value: "{scratch_base_path}/{name}_{variant}-{flow}-{tool}" + } + { + name: rel_path + value: "hw/ip/{name}_{variant}/dv" + } + ] + + // Default UVM test and seq class name. + uvm_test: sram_ctrl_base_test + uvm_test_seq: sram_ctrl_base_vseq + + // Increase timeout for all tests and enable cdc instrumentation. + run_opts: ["+test_timeout_ns=1000000000", + "+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: "{name}_smoke" + uvm_test_seq: sram_ctrl_smoke_vseq + } + { + name: "{name}_multiple_keys" + uvm_test_seq: sram_ctrl_multiple_keys_vseq + } + { + name: "{name}_bijection" + uvm_test_seq: sram_ctrl_bijection_vseq + // We max. do 25*32768 write and 25*32768 read operations. Each operation + // takes roughly 1000ns, resulting in 1638400ns for the read/write + // operations. Add some buffer for setting up the test and requesting + // new scrambling keys. + run_opts: ["+test_timeout_ns=2000000000"] + } + { + name: "{name}_stress_pipeline" + uvm_test_seq: sram_ctrl_stress_pipeline_vseq + run_opts: ["+zero_delays=1"] + } + { + name: "{name}_partial_access" + uvm_test_seq: sram_ctrl_smoke_vseq + run_opts: ["+partial_access_pct=90"] + } + { + name: "{name}_partial_access_b2b" + uvm_test_seq: sram_ctrl_stress_pipeline_vseq + run_opts: ["+partial_access_pct=90"] + } + { + name: "{name}_max_throughput" + uvm_test_seq: sram_ctrl_throughput_vseq + run_opts: ["+zero_delays=1 +partial_access_pct=0"] + } + { + name: "{name}_throughput_w_partial_write" + uvm_test_seq: sram_ctrl_throughput_vseq + run_opts: ["+zero_delays=1 +partial_access_pct=20"] + } + { + name: "{name}_throughput_w_readback" + uvm_test_seq: sram_ctrl_throughput_vseq + run_opts: ["+zero_delays=1 +partial_access_pct=0 +init_w_readback=1"] + } + { + name: "{name}_lc_escalation" + uvm_test_seq: sram_ctrl_lc_escalation_vseq + } + { + name: "{name}_access_during_key_req" + uvm_test_seq: sram_ctrl_access_during_key_req_vseq + // Need to make sure no sram access when we just request new key or init, so use zero_delays + run_opts: ["+zero_delays=1"] + } + { + name: "{name}_executable" + uvm_test_seq: sram_ctrl_executable_vseq + } + { + name: "{name}_regwen" + uvm_test_seq: sram_ctrl_regwen_vseq + } + { + name: "{name}_ram_cfg" + uvm_test_seq: "{name}_ram_cfg_vseq" + } + // Below 2 tests are same as the tests in dvsim/tests/mem_tests.hjson + // Replicate them here in order to enable scb + { + name: "{name}_mem_walk" + uvm_test_seq: "{name}_common_vseq" + run_opts: ["+csr_mem_walk"] + } + { + name: "{name}_mem_partial_access" + uvm_test_seq: "{name}_common_vseq" + run_opts: ["+run_mem_partial_access"] + } + { + name: "{name}_readback_err" + uvm_test_seq: sram_ctrl_readback_err_vseq + } + { + name: "{name}_mubi_enc_err" + uvm_test_seq: sram_ctrl_mubi_enc_err_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["{name}_smoke"] + } + ] +} diff --git a/hw/ip/sram_ctrl/dv/sram_ctrl_fi_sim.core b/hw/ip/sram_ctrl/dv/sram_ctrl_fi_sim.core new file mode 100644 index 0000000000000..0b17cd0cfcc25 --- /dev/null +++ b/hw/ip/sram_ctrl/dv/sram_ctrl_fi_sim.core @@ -0,0 +1,46 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:sram_ctrl_fi_sim:0.1" +description: "SRAM_CTRL DV FI sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:sram_ctrl + - lowrisc:prim:ram_1p_scr + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:dv:sram_ctrl_bkdr_util + - lowrisc:dv:sram_ctrl_test + - lowrisc:dv:sram_ctrl_sva + files: + - tb.sv + - cov/sram_ctrl_cov_bind.sv + file_type: systemVerilogSource + + files_fi_strobe: + files: + - fi/strobe.sv + file_type: systemVerilogSource + + files_fi_sff: + files: + - fi/block.sff + - fi/project.sff + file_type: standardFaultFormat + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + - files_fi_strobe + - files_fi_sff + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/ip/sram_ctrl/dv/sram_ctrl_main_fi_sim_cfg.hjson b/hw/ip/sram_ctrl/dv/sram_ctrl_main_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..799cdd24673d1 --- /dev/null +++ b/hw/ip/sram_ctrl/dv/sram_ctrl_main_fi_sim_cfg.hjson @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// sim cfg file for the main SRAM variant +{ + // Name of the sim cfg variant + variant: main + + // Import the base sram_ctrl sim_cfg file + import_cfgs: ["{proj_root}/hw/ip/sram_ctrl/dv/sram_ctrl_base_fi_sim_cfg.hjson"] + + // These parameters are used for top_earlgrey main sram + build_opts: ["+define+SRAM_WORD_ADDR_WIDTH=15", + "+define+INSTR_EXEC=1", + "+define+NUM_PRINCE_ROUNDS_HALF=2"] + + fi_core: "lowrisc:dv:sram_ctrl_fi_sim:0.1" + fi_src_dir: "{eval_cmd} echo \"{fi_core}\" | tr ':' '_'" + + block_sff_file: "{fi_src_dir}/fi/block.sff" + project_sff_file: "{fi_src_dir}/fi/project.sff" + strobe_file: "{fi_src_dir}/fi/strobe.sv" +} diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv index be9576375325f..93a29f4fe7b94 100644 --- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv +++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv @@ -767,4 +767,25 @@ module sram_ctrl // because the SRAM is initializing. `ASSERT(TlulGntIsCorrect_A, tlul_req |-> (sram_gnt & ~init_req) == tlul_gnt) + `ifdef FI_SIM_Z01X + // Check if there are any TL-UL integrity errors caused by faults that Z01X has introduced. + // Specific to fault injection simulation as Z01X expects that those strobing points are + // available in the design. + wire ram_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_ram ( + .tl_i (ram_tl_o), + .err_o(ram_tl_intg_err) + ); + + wire regs_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_regs ( + .tl_i (regs_tl_o), + .err_o(regs_tl_intg_err) + ); + `endif + endmodule : sram_ctrl diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson.tpl new file mode 100644 index 0000000000000..6d6af0b8b44df --- /dev/null +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson.tpl @@ -0,0 +1,500 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: flash_ctrl + + // Top level dut name (sv module). + dut: flash_ctrl + + // Top level testbench name (sv module). + tb: tb + + // Fusesoc core file used for building the file list. + fusesoc_core: ${instance_vlnv("lowrisc:dv:flash_ctrl_fi_sim:0.1")} + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for crypto_dpi_prince + "{proj_root}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"], + + en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"] + // Flash references pwrmgr directly, need to reference the top version + overrides: [ + { + name: "timescale" + value: "1ns/100ps" + } + ] + + // Add additional tops for simulation. + sim_tops: ["strobe"] + + // Default iterations for all tests - each test entry can override this. + reseed: 1 + + + run_modes: [ + { + name: csr_tests_mode + run_opts: ["+csr_test_mode=1"] + } + ] + + // Add default run opt + run_opts: ["+flash_rand_delay_en=1"] + + // Default UVM test and seq class name. + uvm_test: flash_ctrl_base_test + uvm_test_seq: flash_ctrl_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: flash_ctrl_smoke + uvm_test_seq: flash_ctrl_smoke_vseq + reseed: 50 + } + { + name: flash_ctrl_smoke_hw + uvm_test_seq: flash_ctrl_smoke_hw_vseq + reseed: 5 + } + { + name: flash_ctrl_rand_ops + uvm_test_seq: flash_ctrl_rand_ops_vseq + reseed: 20 + } + { + name: flash_ctrl_sw_op + uvm_test_seq: flash_ctrl_sw_op_vseq + reseed: 5 + } + { + name: flash_ctrl_host_dir_rd + uvm_test_seq: flash_ctrl_host_dir_rd_vseq + run_opts: ["+zero_delays=1"] + reseed: 5 + } + { + name: flash_ctrl_rd_buff_evict + uvm_test_seq: flash_ctrl_rd_buff_evict_vseq + run_opts: ["+en_cov=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_arb + uvm_test_seq: flash_ctrl_phy_arb_vseq + run_opts: ["+zero_delays=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_sec_otp + uvm_test_seq: flash_ctrl_hw_sec_otp_vseq + run_opts: ["+test_timeout_ns=300_000_000_000"] + reseed: 50 + } + { + name: flash_ctrl_erase_suspend + uvm_test_seq: flash_ctrl_erase_suspend_vseq + run_opts: ["+zero_delays=1"] + reseed: 5 + } + { + name: flash_ctrl_hw_rma + uvm_test_seq: flash_ctrl_hw_rma_vseq + run_opts: ["+flash_program_latency=5", "+test_timeout_ns=300_000_000_000"] + reseed: 3 + } + { + name: flash_ctrl_hw_rma_reset + uvm_test_seq: flash_ctrl_hw_rma_reset_vseq + run_opts: ["+flash_program_latency=5", "+test_timeout_ns=300_000_000_000"] + reseed: 20 + } + { + name: flash_ctrl_otp_reset + uvm_test_seq: flash_ctrl_otp_reset_vseq + run_opts: ["+test_timeout_ns=300_000_000_000"] + reseed: 80 + } + { + name: flash_ctrl_host_ctrl_arb + uvm_test_seq: flash_ctrl_host_ctrl_arb_vseq + run_opts: ["+zero_delays=1", "+test_timeout_ns=300_000_000_000"] + reseed: 5 + } + { + name: flash_ctrl_mp_regions + uvm_test_seq: flash_ctrl_mp_regions_vseq + run_opts: ["+multi_alert=1", "+test_timeout_ns=300_000_000_000", + "+fast_rcvr_recov_err", "+op_readonly_on_info1_partition=0"] + reseed: 20 + } + { + name: flash_ctrl_fetch_code + uvm_test_seq: flash_ctrl_fetch_code_vseq + run_opts: ["+op_readonly_on_info_partition=1", + "+op_readonly_on_info1_partition=1"] + reseed: 10 + } + { + name: flash_ctrl_full_mem_access + uvm_test_seq: flash_ctrl_full_mem_access_vseq + run_opts: ["+test_timeout_ns=500_000_000_000"] + reseed: 5 + run_timeout_mins: 180 + } + { + name: flash_ctrl_error_prog_type + uvm_test_seq: flash_ctrl_error_prog_type_vseq + run_opts: ["+op_readonly_on_info_partition=1", + "+op_readonly_on_info1_partition=1"] + reseed: 5 + } + { + name: flash_ctrl_error_prog_win + uvm_test_seq: flash_ctrl_error_prog_win_vseq + reseed: 10 + } + { + name: flash_ctrl_error_mp + uvm_test_seq: flash_ctrl_error_mp_vseq + run_opts: ["+test_timeout_ns=300_000_000_000", "+op_readonly_on_info_partition=0", + "+op_readonly_on_info1_partition=0", "+op_readonly_on_info2_partition=0"] + reseed: 10 + } + { + name: flash_ctrl_invalid_op + uvm_test_seq: flash_ctrl_invalid_op_vseq + run_opts: ["+fast_rcvr_recov_err"] + reseed: 20 + } + { + name: flash_ctrl_mid_op_rst + uvm_test_seq: flash_ctrl_mid_op_rst_vseq + reseed: 5 + } + { + name: flash_ctrl_wo + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=100", "+otf_num_hr=0", "+otf_rd_pct=0", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_write_word_sweep + uvm_test_seq: flash_ctrl_write_word_sweep_vseq + run_opts: ["+scb_otf_en=1"] + reseed: 1 + } + { + name: flash_ctrl_read_word_sweep + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1"] + reseed: 1 + } + { + name: flash_ctrl_ro + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_rw + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+test_timeout_ns=5_000_000_000", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_read_word_sweep_serr + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3"] + reseed: 5 + } + { + name: flash_ctrl_ro_serr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0"] + reseed: 10 + } + { + name: flash_ctrl_rw_serr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000"] + reseed: 10 + } + { + name: flash_ctrl_serr_counter + uvm_test_seq: flash_ctrl_serr_counter_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=1", + "+otf_num_rw=50", "+otf_num_hr=5"] + reseed: 5 + } + { + name: flash_ctrl_serr_address + uvm_test_seq: flash_ctrl_serr_address_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=1", + "+otf_num_rw=5", "+otf_num_hr=0"] + reseed: 5 + } + { + name: flash_ctrl_read_word_sweep_derr + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_ro_derr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0", + "+bypass_alert_ready_to_end_check=1"] + reseed: 10 + } + { + name: flash_ctrl_rw_derr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", + "+bypass_alert_ready_to_end_check=1"] + reseed: 10 + } + { + name: flash_ctrl_derr_detect + uvm_test_seq: flash_ctrl_derr_detect_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=4", + "+otf_num_rw=50", "+otf_num_hr=200", + "+rerun=5", "+otf_wr_pct=1"] + reseed: 5 + } + { + name: flash_ctrl_oversize_error + uvm_test_seq: flash_ctrl_oversize_error_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=0", + "+otf_num_hr=1000", "+otf_num_rw=100", + "+otf_wr_pct=4", "+otf_rd_pct=4"] + reseed: 5 + } + { + name: flash_ctrl_integrity + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=4", "+ierr_pct=3", + "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_intr_rd + uvm_test_seq: flash_ctrl_intr_rd_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 40 + } + { + name: flash_ctrl_intr_wr + uvm_test_seq: flash_ctrl_intr_wr_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"] + reseed: 10 + } + { + name: flash_ctrl_intr_rd_slow_flash + uvm_test_seq: flash_ctrl_intr_rd_vseq + run_opts: ["+scb_otf_en=1", "+flash_read_latency=50", "+flash_program_latency=500", "+test_timeout_ns=500_000_000"] + reseed: 40 + } + { + name: flash_ctrl_intr_wr_slow_flash + uvm_test_seq: flash_ctrl_intr_wr_vseq + run_opts: ["+scb_otf_en=1", "+flash_read_latency=50", "+flash_program_latency=500", + "+rd_buf_en_to=500_000", "+test_timeout_ns=1_000_000_000"] + reseed: 10 + } + { + name: flash_ctrl_prog_reset + uvm_test_seq: flash_ctrl_prog_reset_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"] + reseed: 30 + } + { + name: flash_ctrl_rw_evict + uvm_test_seq: flash_ctrl_rw_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 40 + } + { + name: flash_ctrl_rw_evict_all_en + uvm_test_seq: flash_ctrl_rw_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1", + "+en_always_prog=1", "+en_rnd_data=0"] + reseed: 40 + } + { + name: flash_ctrl_re_evict + uvm_test_seq: flash_ctrl_re_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 20 + } + { + name: flash_ctrl_disable + uvm_test_seq: flash_ctrl_disable_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+en_always_all=1", + "+bypass_alert_ready_to_end_check=1"] + reseed: 50 + } + { + name: flash_ctrl_sec_cm + run_timeout_mins: 180 + } + { + name: flash_ctrl_sec_info_access + uvm_test_seq: flash_ctrl_info_part_access_vseq + reseed: 50 + } + { + name: flash_ctrl_stress_all + reseed: 5 + } + { + name: flash_ctrl_connect + uvm_test_seq: flash_ctrl_connect_vseq + reseed: 80 + } + { + name: flash_ctrl_rd_intg + uvm_test_seq: flash_ctrl_rd_path_intg_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+otf_num_hr=100", "+en_always_read=1"] + reseed: 3 + } + { + name: flash_ctrl_wr_intg + uvm_test_seq: flash_ctrl_wr_path_intg_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=10", "+otf_num_hr=0", "+ecc_mode=1", + "+en_always_prog=1", "+otf_rd_pct=0"] + reseed: 3 + } + { + name: flash_ctrl_access_after_disable + uvm_test_seq: flash_ctrl_access_after_disable_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+otf_num_rw=5", "+otf_num_hr=0", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 3 + } + { + name: flash_ctrl_fs_sup + uvm_test_seq: flash_ctrl_filesystem_support_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_all=1", "+en_all_info_acc=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_arb_redun + uvm_test_seq: flash_ctrl_phy_arb_redun_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=10", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_host_grant_err + uvm_test_seq: flash_ctrl_phy_host_grant_err_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=50", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_ack_consistency + uvm_test_seq: flash_ctrl_phy_ack_consistency_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=10", "+ecc_mode=1", "+bank0_pct=8", + "+otf_rd_pct=4", "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_config_regwen + uvm_test_seq: flash_ctrl_config_regwen_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_all=1"] + reseed: 5 + } + { + name: flash_ctrl_rma_err + uvm_test_seq: flash_ctrl_hw_rma_err_vseq + run_opts: ["+flash_program_latency=5", "+flash_erase_latency=50", "+test_timeout_ns=300_000_000_000"] + reseed: 3 + } + { + name: flash_ctrl_lcmgr_intg + uvm_test_seq: flash_ctrl_lcmgr_intg_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_read_seed_err + uvm_test_seq: flash_ctrl_hw_read_seed_err_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_prog_rma_wipe_err + uvm_test_seq: flash_ctrl_hw_prog_rma_wipe_err_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+flash_program_latency=5", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_rd_ooo + uvm_test_seq: flash_ctrl_rd_ooo_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=10", "+otf_num_hr=100", + "+ecc_mode=1"] + reseed: 1 + } + { + name: flash_ctrl_host_addr_infection + uvm_test_seq: flash_ctrl_host_addr_infection_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+otf_num_hr=100", "+en_always_read=1"] + reseed: 3 + } + { + name: flash_ctrl_basic_rw + uvm_test_seq: flash_ctrl_basic_rw_vseq + reseed: 3 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["flash_ctrl_smoke"] + } + { + // For test clean up run subset of tests + name: evict + tests: ["flash_ctrl_rw_evict", + "flash_ctrl_re_evict", + "flash_ctrl_rw_evict_all_en" + ] + } + { + name: flash_err + tests: ["flash_ctrl_error_mp", "flash_ctrl_error_prog_win", + "flash_ctrl_error_prog_type" + ] + } + ] +} diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_fi_sim.core.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_fi_sim.core.tpl new file mode 100644 index 0000000000000..34dd6c0154dd3 --- /dev/null +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_fi_sim.core.tpl @@ -0,0 +1,47 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:dv:flash_ctrl_fi_sim:0.1")} +description: "FLASH_CTRL DV FI sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - ${instance_vlnv("lowrisc:constants:top_pkg")} + - ${instance_vlnv("lowrisc:ip:flash_ctrl:0.1")} + file_type: systemVerilogSource + + files_dv: + depend: + - ${instance_vlnv("lowrisc:dv:flash_ctrl_bkdr_util")} + - ${instance_vlnv("lowrisc:dv:flash_ctrl_test")} + - ${instance_vlnv("lowrisc:dv:flash_ctrl_sva")} + - ${instance_vlnv("lowrisc:dv:flash_ctrl_cov")} + files: + - tb/tb.sv + file_type: systemVerilogSource + + files_fi_strobe: + files: + - fi/strobe.sv + file_type: systemVerilogSource + + files_fi_sff: + files: + - fi/block.sff + - fi/project.sff + file_type: standardFaultFormat + +targets: + default: &default_target + toplevel: tb + filesets: + - files_rtl + - files_dv + - files_fi_strobe + - files_fi_sff + + sim: + <<: *default_target + default_tool: vcs diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..74cf0e8d098c6 --- /dev/null +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// We want to use a different tool in another flash_ctrl env, but overriding `tool` doesn't work, as +// it needs to first import all the included hjson to know what to override, but some fi_sim_cfg hjson +// files depends on the `tool` variable, such as {tool}.hjson. +// To solve this issue, split out the fi_sim_cfg file into 2 files. the base contains everything except +// `tool`, the other one includes the base and set the `tool`. +// +// In this file, only `tool` can be set. Tests or other configuration should be add in +// flash_ctrl_base_fi_sim_cfg.hjson. +{ + // FI Simulator used to sign off this block + tool: z01x + + import_cfgs: ["{self_dir}/flash_ctrl_base_fi_sim_cfg.hjson"] + + fi_core: "lowrisc:earlgrey_dv:flash_ctrl_fi_sim:0.1" + fi_src_dir: "{eval_cmd} echo \"{fi_core}\" | tr ':' '_'" + + block_sff_file: "{fi_src_dir}/fi/block.sff" + project_sff_file: "{fi_src_dir}/fi/project.sff" + strobe_file: "{fi_src_dir}/fi/strobe.sv" +} diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl index a23f2a230c721..11b4b5438446e 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl +++ b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl @@ -1491,4 +1491,33 @@ module flash_ctrl // Alert assertions for reg_we onehot check `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1]) + `ifdef FI_SIM_Z01X + // Check if there are any TL-UL integrity errors caused by faults that Z01X has introduced. + // Specific to fault injection simulation as Z01X expects that those strobing points are + // available in the design. + wire mem_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_mem ( + .tl_i (mem_tl_o), + .err_o(mem_tl_intg_err) + ); + + wire prim_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_prim ( + .tl_i (prim_tl_o), + .err_o(prim_tl_intg_err) + ); + + wire core_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_core ( + .tl_i (core_tl_o), + .err_o(core_tl_intg_err) + ); + `endif + endmodule diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..1d4c3f7b7fbfa --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson @@ -0,0 +1,500 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: flash_ctrl + + // Top level dut name (sv module). + dut: flash_ctrl + + // Top level testbench name (sv module). + tb: tb + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:earlgrey_dv:flash_ctrl_fi_sim:0.1 + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for crypto_dpi_prince + "{proj_root}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"], + + en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"] + // Flash references pwrmgr directly, need to reference the top version + overrides: [ + { + name: "timescale" + value: "1ns/100ps" + } + ] + + // Add additional tops for simulation. + sim_tops: ["strobe"] + + // Default iterations for all tests - each test entry can override this. + reseed: 1 + + + run_modes: [ + { + name: csr_tests_mode + run_opts: ["+csr_test_mode=1"] + } + ] + + // Add default run opt + run_opts: ["+flash_rand_delay_en=1"] + + // Default UVM test and seq class name. + uvm_test: flash_ctrl_base_test + uvm_test_seq: flash_ctrl_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: flash_ctrl_smoke + uvm_test_seq: flash_ctrl_smoke_vseq + reseed: 50 + } + { + name: flash_ctrl_smoke_hw + uvm_test_seq: flash_ctrl_smoke_hw_vseq + reseed: 5 + } + { + name: flash_ctrl_rand_ops + uvm_test_seq: flash_ctrl_rand_ops_vseq + reseed: 20 + } + { + name: flash_ctrl_sw_op + uvm_test_seq: flash_ctrl_sw_op_vseq + reseed: 5 + } + { + name: flash_ctrl_host_dir_rd + uvm_test_seq: flash_ctrl_host_dir_rd_vseq + run_opts: ["+zero_delays=1"] + reseed: 5 + } + { + name: flash_ctrl_rd_buff_evict + uvm_test_seq: flash_ctrl_rd_buff_evict_vseq + run_opts: ["+en_cov=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_arb + uvm_test_seq: flash_ctrl_phy_arb_vseq + run_opts: ["+zero_delays=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_sec_otp + uvm_test_seq: flash_ctrl_hw_sec_otp_vseq + run_opts: ["+test_timeout_ns=300_000_000_000"] + reseed: 50 + } + { + name: flash_ctrl_erase_suspend + uvm_test_seq: flash_ctrl_erase_suspend_vseq + run_opts: ["+zero_delays=1"] + reseed: 5 + } + { + name: flash_ctrl_hw_rma + uvm_test_seq: flash_ctrl_hw_rma_vseq + run_opts: ["+flash_program_latency=5", "+test_timeout_ns=300_000_000_000"] + reseed: 3 + } + { + name: flash_ctrl_hw_rma_reset + uvm_test_seq: flash_ctrl_hw_rma_reset_vseq + run_opts: ["+flash_program_latency=5", "+test_timeout_ns=300_000_000_000"] + reseed: 20 + } + { + name: flash_ctrl_otp_reset + uvm_test_seq: flash_ctrl_otp_reset_vseq + run_opts: ["+test_timeout_ns=300_000_000_000"] + reseed: 80 + } + { + name: flash_ctrl_host_ctrl_arb + uvm_test_seq: flash_ctrl_host_ctrl_arb_vseq + run_opts: ["+zero_delays=1", "+test_timeout_ns=300_000_000_000"] + reseed: 5 + } + { + name: flash_ctrl_mp_regions + uvm_test_seq: flash_ctrl_mp_regions_vseq + run_opts: ["+multi_alert=1", "+test_timeout_ns=300_000_000_000", + "+fast_rcvr_recov_err", "+op_readonly_on_info1_partition=0"] + reseed: 20 + } + { + name: flash_ctrl_fetch_code + uvm_test_seq: flash_ctrl_fetch_code_vseq + run_opts: ["+op_readonly_on_info_partition=1", + "+op_readonly_on_info1_partition=1"] + reseed: 10 + } + { + name: flash_ctrl_full_mem_access + uvm_test_seq: flash_ctrl_full_mem_access_vseq + run_opts: ["+test_timeout_ns=500_000_000_000"] + reseed: 5 + run_timeout_mins: 180 + } + { + name: flash_ctrl_error_prog_type + uvm_test_seq: flash_ctrl_error_prog_type_vseq + run_opts: ["+op_readonly_on_info_partition=1", + "+op_readonly_on_info1_partition=1"] + reseed: 5 + } + { + name: flash_ctrl_error_prog_win + uvm_test_seq: flash_ctrl_error_prog_win_vseq + reseed: 10 + } + { + name: flash_ctrl_error_mp + uvm_test_seq: flash_ctrl_error_mp_vseq + run_opts: ["+test_timeout_ns=300_000_000_000", "+op_readonly_on_info_partition=0", + "+op_readonly_on_info1_partition=0", "+op_readonly_on_info2_partition=0"] + reseed: 10 + } + { + name: flash_ctrl_invalid_op + uvm_test_seq: flash_ctrl_invalid_op_vseq + run_opts: ["+fast_rcvr_recov_err"] + reseed: 20 + } + { + name: flash_ctrl_mid_op_rst + uvm_test_seq: flash_ctrl_mid_op_rst_vseq + reseed: 5 + } + { + name: flash_ctrl_wo + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=100", "+otf_num_hr=0", "+otf_rd_pct=0", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_write_word_sweep + uvm_test_seq: flash_ctrl_write_word_sweep_vseq + run_opts: ["+scb_otf_en=1"] + reseed: 1 + } + { + name: flash_ctrl_read_word_sweep + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1"] + reseed: 1 + } + { + name: flash_ctrl_ro + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_rw + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+test_timeout_ns=5_000_000_000", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_read_word_sweep_serr + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3"] + reseed: 5 + } + { + name: flash_ctrl_ro_serr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0"] + reseed: 10 + } + { + name: flash_ctrl_rw_serr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000"] + reseed: 10 + } + { + name: flash_ctrl_serr_counter + uvm_test_seq: flash_ctrl_serr_counter_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=1", + "+otf_num_rw=50", "+otf_num_hr=5"] + reseed: 5 + } + { + name: flash_ctrl_serr_address + uvm_test_seq: flash_ctrl_serr_address_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=1", + "+otf_num_rw=5", "+otf_num_hr=0"] + reseed: 5 + } + { + name: flash_ctrl_read_word_sweep_derr + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_ro_derr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0", + "+bypass_alert_ready_to_end_check=1"] + reseed: 10 + } + { + name: flash_ctrl_rw_derr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", + "+bypass_alert_ready_to_end_check=1"] + reseed: 10 + } + { + name: flash_ctrl_derr_detect + uvm_test_seq: flash_ctrl_derr_detect_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=4", + "+otf_num_rw=50", "+otf_num_hr=200", + "+rerun=5", "+otf_wr_pct=1"] + reseed: 5 + } + { + name: flash_ctrl_oversize_error + uvm_test_seq: flash_ctrl_oversize_error_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=0", + "+otf_num_hr=1000", "+otf_num_rw=100", + "+otf_wr_pct=4", "+otf_rd_pct=4"] + reseed: 5 + } + { + name: flash_ctrl_integrity + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=4", "+ierr_pct=3", + "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_intr_rd + uvm_test_seq: flash_ctrl_intr_rd_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 40 + } + { + name: flash_ctrl_intr_wr + uvm_test_seq: flash_ctrl_intr_wr_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"] + reseed: 10 + } + { + name: flash_ctrl_intr_rd_slow_flash + uvm_test_seq: flash_ctrl_intr_rd_vseq + run_opts: ["+scb_otf_en=1", "+flash_read_latency=50", "+flash_program_latency=500", "+test_timeout_ns=500_000_000"] + reseed: 40 + } + { + name: flash_ctrl_intr_wr_slow_flash + uvm_test_seq: flash_ctrl_intr_wr_vseq + run_opts: ["+scb_otf_en=1", "+flash_read_latency=50", "+flash_program_latency=500", + "+rd_buf_en_to=500_000", "+test_timeout_ns=1_000_000_000"] + reseed: 10 + } + { + name: flash_ctrl_prog_reset + uvm_test_seq: flash_ctrl_prog_reset_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"] + reseed: 30 + } + { + name: flash_ctrl_rw_evict + uvm_test_seq: flash_ctrl_rw_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 40 + } + { + name: flash_ctrl_rw_evict_all_en + uvm_test_seq: flash_ctrl_rw_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1", + "+en_always_prog=1", "+en_rnd_data=0"] + reseed: 40 + } + { + name: flash_ctrl_re_evict + uvm_test_seq: flash_ctrl_re_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 20 + } + { + name: flash_ctrl_disable + uvm_test_seq: flash_ctrl_disable_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+en_always_all=1", + "+bypass_alert_ready_to_end_check=1"] + reseed: 50 + } + { + name: flash_ctrl_sec_cm + run_timeout_mins: 180 + } + { + name: flash_ctrl_sec_info_access + uvm_test_seq: flash_ctrl_info_part_access_vseq + reseed: 50 + } + { + name: flash_ctrl_stress_all + reseed: 5 + } + { + name: flash_ctrl_connect + uvm_test_seq: flash_ctrl_connect_vseq + reseed: 80 + } + { + name: flash_ctrl_rd_intg + uvm_test_seq: flash_ctrl_rd_path_intg_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+otf_num_hr=100", "+en_always_read=1"] + reseed: 3 + } + { + name: flash_ctrl_wr_intg + uvm_test_seq: flash_ctrl_wr_path_intg_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=10", "+otf_num_hr=0", "+ecc_mode=1", + "+en_always_prog=1", "+otf_rd_pct=0"] + reseed: 3 + } + { + name: flash_ctrl_access_after_disable + uvm_test_seq: flash_ctrl_access_after_disable_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+otf_num_rw=5", "+otf_num_hr=0", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 3 + } + { + name: flash_ctrl_fs_sup + uvm_test_seq: flash_ctrl_filesystem_support_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_all=1", "+en_all_info_acc=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_arb_redun + uvm_test_seq: flash_ctrl_phy_arb_redun_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=10", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_host_grant_err + uvm_test_seq: flash_ctrl_phy_host_grant_err_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=50", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_ack_consistency + uvm_test_seq: flash_ctrl_phy_ack_consistency_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=10", "+ecc_mode=1", "+bank0_pct=8", + "+otf_rd_pct=4", "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_config_regwen + uvm_test_seq: flash_ctrl_config_regwen_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_all=1"] + reseed: 5 + } + { + name: flash_ctrl_rma_err + uvm_test_seq: flash_ctrl_hw_rma_err_vseq + run_opts: ["+flash_program_latency=5", "+flash_erase_latency=50", "+test_timeout_ns=300_000_000_000"] + reseed: 3 + } + { + name: flash_ctrl_lcmgr_intg + uvm_test_seq: flash_ctrl_lcmgr_intg_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_read_seed_err + uvm_test_seq: flash_ctrl_hw_read_seed_err_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_prog_rma_wipe_err + uvm_test_seq: flash_ctrl_hw_prog_rma_wipe_err_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+flash_program_latency=5", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_rd_ooo + uvm_test_seq: flash_ctrl_rd_ooo_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=10", "+otf_num_hr=100", + "+ecc_mode=1"] + reseed: 1 + } + { + name: flash_ctrl_host_addr_infection + uvm_test_seq: flash_ctrl_host_addr_infection_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+otf_num_hr=100", "+en_always_read=1"] + reseed: 3 + } + { + name: flash_ctrl_basic_rw + uvm_test_seq: flash_ctrl_basic_rw_vseq + reseed: 3 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["flash_ctrl_smoke"] + } + { + // For test clean up run subset of tests + name: evict + tests: ["flash_ctrl_rw_evict", + "flash_ctrl_re_evict", + "flash_ctrl_rw_evict_all_en" + ] + } + { + name: flash_err + tests: ["flash_ctrl_error_mp", "flash_ctrl_error_prog_win", + "flash_ctrl_error_prog_type" + ] + } + ] +} diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim.core new file mode 100644 index 0000000000000..4648f75eb3ca5 --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim.core @@ -0,0 +1,47 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:earlgrey_dv:flash_ctrl_fi_sim:0.1 +description: "FLASH_CTRL DV FI sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:earlgrey_constants:top_pkg + - lowrisc:earlgrey_ip:flash_ctrl:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:earlgrey_dv:flash_ctrl_bkdr_util + - lowrisc:earlgrey_dv:flash_ctrl_test + - lowrisc:earlgrey_dv:flash_ctrl_sva + - lowrisc:earlgrey_dv:flash_ctrl_cov + files: + - tb/tb.sv + file_type: systemVerilogSource + + files_fi_strobe: + files: + - fi/strobe.sv + file_type: systemVerilogSource + + files_fi_sff: + files: + - fi/block.sff + - fi/project.sff + file_type: standardFaultFormat + +targets: + default: &default_target + toplevel: tb + filesets: + - files_rtl + - files_dv + - files_fi_strobe + - files_fi_sff + + sim: + <<: *default_target + default_tool: vcs diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..74cf0e8d098c6 --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// We want to use a different tool in another flash_ctrl env, but overriding `tool` doesn't work, as +// it needs to first import all the included hjson to know what to override, but some fi_sim_cfg hjson +// files depends on the `tool` variable, such as {tool}.hjson. +// To solve this issue, split out the fi_sim_cfg file into 2 files. the base contains everything except +// `tool`, the other one includes the base and set the `tool`. +// +// In this file, only `tool` can be set. Tests or other configuration should be add in +// flash_ctrl_base_fi_sim_cfg.hjson. +{ + // FI Simulator used to sign off this block + tool: z01x + + import_cfgs: ["{self_dir}/flash_ctrl_base_fi_sim_cfg.hjson"] + + fi_core: "lowrisc:earlgrey_dv:flash_ctrl_fi_sim:0.1" + fi_src_dir: "{eval_cmd} echo \"{fi_core}\" | tr ':' '_'" + + block_sff_file: "{fi_src_dir}/fi/block.sff" + project_sff_file: "{fi_src_dir}/fi/project.sff" + strobe_file: "{fi_src_dir}/fi/strobe.sv" +} diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv index 32263ee71acb9..d6396d5b4ea60 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv @@ -1492,4 +1492,33 @@ module flash_ctrl // Alert assertions for reg_we onehot check `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1]) + `ifdef FI_SIM_Z01X + // Check if there are any TL-UL integrity errors caused by faults that Z01X has introduced. + // Specific to fault injection simulation as Z01X expects that those strobing points are + // available in the design. + wire mem_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_mem ( + .tl_i (mem_tl_o), + .err_o(mem_tl_intg_err) + ); + + wire prim_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_prim ( + .tl_i (prim_tl_o), + .err_o(prim_tl_intg_err) + ); + + wire core_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_core ( + .tl_i (core_tl_o), + .err_o(core_tl_intg_err) + ); + `endif + endmodule diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..32f672bcc72ba --- /dev/null +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_base_fi_sim_cfg.hjson @@ -0,0 +1,500 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: flash_ctrl + + // Top level dut name (sv module). + dut: flash_ctrl + + // Top level testbench name (sv module). + tb: tb + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:englishbreakfast_dv:flash_ctrl_fi_sim:0.1 + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for crypto_dpi_prince + "{proj_root}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"], + + en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"] + // Flash references pwrmgr directly, need to reference the top version + overrides: [ + { + name: "timescale" + value: "1ns/100ps" + } + ] + + // Add additional tops for simulation. + sim_tops: ["strobe"] + + // Default iterations for all tests - each test entry can override this. + reseed: 1 + + + run_modes: [ + { + name: csr_tests_mode + run_opts: ["+csr_test_mode=1"] + } + ] + + // Add default run opt + run_opts: ["+flash_rand_delay_en=1"] + + // Default UVM test and seq class name. + uvm_test: flash_ctrl_base_test + uvm_test_seq: flash_ctrl_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: flash_ctrl_smoke + uvm_test_seq: flash_ctrl_smoke_vseq + reseed: 50 + } + { + name: flash_ctrl_smoke_hw + uvm_test_seq: flash_ctrl_smoke_hw_vseq + reseed: 5 + } + { + name: flash_ctrl_rand_ops + uvm_test_seq: flash_ctrl_rand_ops_vseq + reseed: 20 + } + { + name: flash_ctrl_sw_op + uvm_test_seq: flash_ctrl_sw_op_vseq + reseed: 5 + } + { + name: flash_ctrl_host_dir_rd + uvm_test_seq: flash_ctrl_host_dir_rd_vseq + run_opts: ["+zero_delays=1"] + reseed: 5 + } + { + name: flash_ctrl_rd_buff_evict + uvm_test_seq: flash_ctrl_rd_buff_evict_vseq + run_opts: ["+en_cov=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_arb + uvm_test_seq: flash_ctrl_phy_arb_vseq + run_opts: ["+zero_delays=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_sec_otp + uvm_test_seq: flash_ctrl_hw_sec_otp_vseq + run_opts: ["+test_timeout_ns=300_000_000_000"] + reseed: 50 + } + { + name: flash_ctrl_erase_suspend + uvm_test_seq: flash_ctrl_erase_suspend_vseq + run_opts: ["+zero_delays=1"] + reseed: 5 + } + { + name: flash_ctrl_hw_rma + uvm_test_seq: flash_ctrl_hw_rma_vseq + run_opts: ["+flash_program_latency=5", "+test_timeout_ns=300_000_000_000"] + reseed: 3 + } + { + name: flash_ctrl_hw_rma_reset + uvm_test_seq: flash_ctrl_hw_rma_reset_vseq + run_opts: ["+flash_program_latency=5", "+test_timeout_ns=300_000_000_000"] + reseed: 20 + } + { + name: flash_ctrl_otp_reset + uvm_test_seq: flash_ctrl_otp_reset_vseq + run_opts: ["+test_timeout_ns=300_000_000_000"] + reseed: 80 + } + { + name: flash_ctrl_host_ctrl_arb + uvm_test_seq: flash_ctrl_host_ctrl_arb_vseq + run_opts: ["+zero_delays=1", "+test_timeout_ns=300_000_000_000"] + reseed: 5 + } + { + name: flash_ctrl_mp_regions + uvm_test_seq: flash_ctrl_mp_regions_vseq + run_opts: ["+multi_alert=1", "+test_timeout_ns=300_000_000_000", + "+fast_rcvr_recov_err", "+op_readonly_on_info1_partition=0"] + reseed: 20 + } + { + name: flash_ctrl_fetch_code + uvm_test_seq: flash_ctrl_fetch_code_vseq + run_opts: ["+op_readonly_on_info_partition=1", + "+op_readonly_on_info1_partition=1"] + reseed: 10 + } + { + name: flash_ctrl_full_mem_access + uvm_test_seq: flash_ctrl_full_mem_access_vseq + run_opts: ["+test_timeout_ns=500_000_000_000"] + reseed: 5 + run_timeout_mins: 180 + } + { + name: flash_ctrl_error_prog_type + uvm_test_seq: flash_ctrl_error_prog_type_vseq + run_opts: ["+op_readonly_on_info_partition=1", + "+op_readonly_on_info1_partition=1"] + reseed: 5 + } + { + name: flash_ctrl_error_prog_win + uvm_test_seq: flash_ctrl_error_prog_win_vseq + reseed: 10 + } + { + name: flash_ctrl_error_mp + uvm_test_seq: flash_ctrl_error_mp_vseq + run_opts: ["+test_timeout_ns=300_000_000_000", "+op_readonly_on_info_partition=0", + "+op_readonly_on_info1_partition=0", "+op_readonly_on_info2_partition=0"] + reseed: 10 + } + { + name: flash_ctrl_invalid_op + uvm_test_seq: flash_ctrl_invalid_op_vseq + run_opts: ["+fast_rcvr_recov_err"] + reseed: 20 + } + { + name: flash_ctrl_mid_op_rst + uvm_test_seq: flash_ctrl_mid_op_rst_vseq + reseed: 5 + } + { + name: flash_ctrl_wo + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=100", "+otf_num_hr=0", "+otf_rd_pct=0", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_write_word_sweep + uvm_test_seq: flash_ctrl_write_word_sweep_vseq + run_opts: ["+scb_otf_en=1"] + reseed: 1 + } + { + name: flash_ctrl_read_word_sweep + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1"] + reseed: 1 + } + { + name: flash_ctrl_ro + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_rw + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+test_timeout_ns=5_000_000_000", "+ecc_mode=1"] + reseed: 20 + } + { + name: flash_ctrl_read_word_sweep_serr + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3"] + reseed: 5 + } + { + name: flash_ctrl_ro_serr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0"] + reseed: 10 + } + { + name: flash_ctrl_rw_serr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000"] + reseed: 10 + } + { + name: flash_ctrl_serr_counter + uvm_test_seq: flash_ctrl_serr_counter_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=1", + "+otf_num_rw=50", "+otf_num_hr=5"] + reseed: 5 + } + { + name: flash_ctrl_serr_address + uvm_test_seq: flash_ctrl_serr_address_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=1", + "+otf_num_rw=5", "+otf_num_hr=0"] + reseed: 5 + } + { + name: flash_ctrl_read_word_sweep_derr + uvm_test_seq: flash_ctrl_read_word_sweep_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_ro_derr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", "+otf_wr_pct=0", + "+bypass_alert_ready_to_end_check=1"] + reseed: 10 + } + { + name: flash_ctrl_rw_derr + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=3", + "+otf_num_rw=100", "+otf_num_hr=1000", + "+bypass_alert_ready_to_end_check=1"] + reseed: 10 + } + { + name: flash_ctrl_derr_detect + uvm_test_seq: flash_ctrl_derr_detect_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=3", "+derr_pct=4", + "+otf_num_rw=50", "+otf_num_hr=200", + "+rerun=5", "+otf_wr_pct=1"] + reseed: 5 + } + { + name: flash_ctrl_oversize_error + uvm_test_seq: flash_ctrl_oversize_error_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+serr_pct=0", + "+otf_num_hr=1000", "+otf_num_rw=100", + "+otf_wr_pct=4", "+otf_rd_pct=4"] + reseed: 5 + } + { + name: flash_ctrl_integrity + uvm_test_seq: flash_ctrl_rw_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=4", "+ierr_pct=3", + "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_intr_rd + uvm_test_seq: flash_ctrl_intr_rd_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 40 + } + { + name: flash_ctrl_intr_wr + uvm_test_seq: flash_ctrl_intr_wr_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"] + reseed: 10 + } + { + name: flash_ctrl_intr_rd_slow_flash + uvm_test_seq: flash_ctrl_intr_rd_vseq + run_opts: ["+scb_otf_en=1", "+flash_read_latency=50", "+flash_program_latency=500", "+test_timeout_ns=500_000_000"] + reseed: 40 + } + { + name: flash_ctrl_intr_wr_slow_flash + uvm_test_seq: flash_ctrl_intr_wr_vseq + run_opts: ["+scb_otf_en=1", "+flash_read_latency=50", "+flash_program_latency=500", + "+rd_buf_en_to=500_000", "+test_timeout_ns=1_000_000_000"] + reseed: 10 + } + { + name: flash_ctrl_prog_reset + uvm_test_seq: flash_ctrl_prog_reset_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"] + reseed: 30 + } + { + name: flash_ctrl_rw_evict + uvm_test_seq: flash_ctrl_rw_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 40 + } + { + name: flash_ctrl_rw_evict_all_en + uvm_test_seq: flash_ctrl_rw_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1", + "+en_always_prog=1", "+en_rnd_data=0"] + reseed: 40 + } + { + name: flash_ctrl_re_evict + uvm_test_seq: flash_ctrl_re_evict_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"] + reseed: 20 + } + { + name: flash_ctrl_disable + uvm_test_seq: flash_ctrl_disable_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=2", "+en_always_all=1", + "+bypass_alert_ready_to_end_check=1"] + reseed: 50 + } + { + name: flash_ctrl_sec_cm + run_timeout_mins: 180 + } + { + name: flash_ctrl_sec_info_access + uvm_test_seq: flash_ctrl_info_part_access_vseq + reseed: 50 + } + { + name: flash_ctrl_stress_all + reseed: 5 + } + { + name: flash_ctrl_connect + uvm_test_seq: flash_ctrl_connect_vseq + reseed: 80 + } + { + name: flash_ctrl_rd_intg + uvm_test_seq: flash_ctrl_rd_path_intg_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+otf_num_hr=100", "+en_always_read=1"] + reseed: 3 + } + { + name: flash_ctrl_wr_intg + uvm_test_seq: flash_ctrl_wr_path_intg_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=10", "+otf_num_hr=0", "+ecc_mode=1", + "+en_always_prog=1", "+otf_rd_pct=0"] + reseed: 3 + } + { + name: flash_ctrl_access_after_disable + uvm_test_seq: flash_ctrl_access_after_disable_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+otf_num_rw=5", "+otf_num_hr=0", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 3 + } + { + name: flash_ctrl_fs_sup + uvm_test_seq: flash_ctrl_filesystem_support_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_all=1", "+en_all_info_acc=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_arb_redun + uvm_test_seq: flash_ctrl_phy_arb_redun_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=10", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_host_grant_err + uvm_test_seq: flash_ctrl_phy_host_grant_err_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=50", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_phy_ack_consistency + uvm_test_seq: flash_ctrl_phy_ack_consistency_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=5", "+otf_num_hr=10", "+ecc_mode=1", "+bank0_pct=8", + "+otf_rd_pct=4", "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 5 + } + { + name: flash_ctrl_config_regwen + uvm_test_seq: flash_ctrl_config_regwen_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_all=1"] + reseed: 5 + } + { + name: flash_ctrl_rma_err + uvm_test_seq: flash_ctrl_hw_rma_err_vseq + run_opts: ["+flash_program_latency=5", "+flash_erase_latency=50", "+test_timeout_ns=300_000_000_000"] + reseed: 3 + } + { + name: flash_ctrl_lcmgr_intg + uvm_test_seq: flash_ctrl_lcmgr_intg_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_read_seed_err + uvm_test_seq: flash_ctrl_hw_read_seed_err_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_hw_prog_rma_wipe_err + uvm_test_seq: flash_ctrl_hw_prog_rma_wipe_err_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+flash_program_latency=5", + "+en_always_all=1", "+bypass_alert_ready_to_end_check=1"] + reseed: 20 + } + { + name: flash_ctrl_rd_ooo + uvm_test_seq: flash_ctrl_rd_ooo_vseq + run_opts: ["+scb_otf_en=1", "+otf_num_rw=10", "+otf_num_hr=100", + "+ecc_mode=1"] + reseed: 1 + } + { + name: flash_ctrl_host_addr_infection + uvm_test_seq: flash_ctrl_host_addr_infection_vseq + run_opts: ["+scb_otf_en=1", "+ecc_mode=1", + "+otf_num_hr=100", "+en_always_read=1"] + reseed: 3 + } + { + name: flash_ctrl_basic_rw + uvm_test_seq: flash_ctrl_basic_rw_vseq + reseed: 3 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["flash_ctrl_smoke"] + } + { + // For test clean up run subset of tests + name: evict + tests: ["flash_ctrl_rw_evict", + "flash_ctrl_re_evict", + "flash_ctrl_rw_evict_all_en" + ] + } + { + name: flash_err + tests: ["flash_ctrl_error_mp", "flash_ctrl_error_prog_win", + "flash_ctrl_error_prog_type" + ] + } + ] +} diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim.core new file mode 100644 index 0000000000000..07121b7eae146 --- /dev/null +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim.core @@ -0,0 +1,47 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:englishbreakfast_dv:flash_ctrl_fi_sim:0.1 +description: "FLASH_CTRL DV FI sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:englishbreakfast_constants:top_pkg + - lowrisc:englishbreakfast_ip:flash_ctrl:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:englishbreakfast_dv:flash_ctrl_bkdr_util + - lowrisc:englishbreakfast_dv:flash_ctrl_test + - lowrisc:englishbreakfast_dv:flash_ctrl_sva + - lowrisc:englishbreakfast_dv:flash_ctrl_cov + files: + - tb/tb.sv + file_type: systemVerilogSource + + files_fi_strobe: + files: + - fi/strobe.sv + file_type: systemVerilogSource + + files_fi_sff: + files: + - fi/block.sff + - fi/project.sff + file_type: standardFaultFormat + +targets: + default: &default_target + toplevel: tb + filesets: + - files_rtl + - files_dv + - files_fi_strobe + - files_fi_sff + + sim: + <<: *default_target + default_tool: vcs diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson new file mode 100644 index 0000000000000..74cf0e8d098c6 --- /dev/null +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_fi_sim_cfg.hjson @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// We want to use a different tool in another flash_ctrl env, but overriding `tool` doesn't work, as +// it needs to first import all the included hjson to know what to override, but some fi_sim_cfg hjson +// files depends on the `tool` variable, such as {tool}.hjson. +// To solve this issue, split out the fi_sim_cfg file into 2 files. the base contains everything except +// `tool`, the other one includes the base and set the `tool`. +// +// In this file, only `tool` can be set. Tests or other configuration should be add in +// flash_ctrl_base_fi_sim_cfg.hjson. +{ + // FI Simulator used to sign off this block + tool: z01x + + import_cfgs: ["{self_dir}/flash_ctrl_base_fi_sim_cfg.hjson"] + + fi_core: "lowrisc:earlgrey_dv:flash_ctrl_fi_sim:0.1" + fi_src_dir: "{eval_cmd} echo \"{fi_core}\" | tr ':' '_'" + + block_sff_file: "{fi_src_dir}/fi/block.sff" + project_sff_file: "{fi_src_dir}/fi/project.sff" + strobe_file: "{fi_src_dir}/fi/strobe.sv" +} diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv index 32263ee71acb9..d6396d5b4ea60 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv @@ -1492,4 +1492,33 @@ module flash_ctrl // Alert assertions for reg_we onehot check `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1]) + `ifdef FI_SIM_Z01X + // Check if there are any TL-UL integrity errors caused by faults that Z01X has introduced. + // Specific to fault injection simulation as Z01X expects that those strobing points are + // available in the design. + wire mem_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_mem ( + .tl_i (mem_tl_o), + .err_o(mem_tl_intg_err) + ); + + wire prim_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_prim ( + .tl_i (prim_tl_o), + .err_o(prim_tl_intg_err) + ); + + wire core_tl_intg_err; + tlul_rsp_intg_chk #( + .EnableRspDataIntgCheck(1) + ) u_rsp_chk_core ( + .tl_i (core_tl_o), + .err_o(core_tl_intg_err) + ); + `endif + endmodule diff --git a/util/dvsim/Deploy.py b/util/dvsim/Deploy.py index 126f28cd6b34a..284345731c030 100644 --- a/util/dvsim/Deploy.py +++ b/util/dvsim/Deploy.py @@ -351,6 +351,7 @@ def _define_attrs(self): "build_dir": False, "build_opts": False, "post_build_cmds": False, + "post_build_opts": False, }) self.mandatory_misc_attrs.update({ @@ -422,6 +423,7 @@ def _define_attrs(self): "build_log": False, "build_timeout_mins": False, "post_build_cmds": False, + "post_build_opts": False, "pre_build_cmds": False, # Report processing diff --git a/util/dvsim/Regression.py b/util/dvsim/Regression.py index 3882702252635..cc270fe9f3cc1 100644 --- a/util/dvsim/Regression.py +++ b/util/dvsim/Regression.py @@ -40,6 +40,7 @@ def __init__(self, regdict): self.pre_run_cmds = [] self.post_run_cmds = [] self.build_opts = [] + self.post_build_opts = [] self.run_opts = [] super().__init__("regression", regdict) @@ -116,6 +117,7 @@ def create_regressions(regdicts, sim_cfg, tests): regression_obj.build_opts.extend(sim_mode_obj.build_opts) regression_obj.pre_run_cmds.extend(sim_mode_obj.pre_run_cmds) regression_obj.post_run_cmds.extend(sim_mode_obj.post_run_cmds) + regression_obj.post_build_opts.extend(sim_mode_obj.post_build_opts) regression_obj.run_opts.extend(sim_mode_obj.run_opts) # Unpack the run_modes @@ -167,6 +169,7 @@ def merge_regression_opts(self): test.build_mode.pre_build_cmds.extend(self.pre_build_cmds) test.build_mode.post_build_cmds.extend(self.post_build_cmds) test.build_mode.build_opts.extend(self.build_opts) + test.build_mode.post_build_opts.extend(self.post_build_opts) processed_build_modes.append(test.build_mode.name) test.pre_run_cmds.extend(self.pre_run_cmds) test.post_run_cmds.extend(self.post_run_cmds) diff --git a/util/dvsim/SimCfg.py b/util/dvsim/SimCfg.py index 5891168a0ea89..07d80f7011148 100644 --- a/util/dvsim/SimCfg.py +++ b/util/dvsim/SimCfg.py @@ -103,6 +103,7 @@ def __init__(self, flow_cfg_file, hjson_data, args, mk_config): self.flow_makefile = "" self.pre_build_cmds = [] self.post_build_cmds = [] + self.post_build_opts = [] self.build_dir = "" self.pre_run_cmds = [] self.post_run_cmds = [] @@ -256,6 +257,7 @@ def _create_objects(self): self.pre_build_cmds.extend(build_mode_obj.pre_build_cmds) self.post_build_cmds.extend(build_mode_obj.post_build_cmds) self.build_opts.extend(build_mode_obj.build_opts) + self.post_build_opts.extend(build_mode_obj.post_build_opts) self.pre_run_cmds.extend(build_mode_obj.pre_run_cmds) self.post_run_cmds.extend(build_mode_obj.post_run_cmds) self.run_opts.extend(build_mode_obj.run_opts) @@ -375,9 +377,9 @@ def _match_items(items: list, patterns: list): # Merge the global build and run opts Test.merge_global_opts(self.run_list, self.pre_build_cmds, self.post_build_cmds, self.build_opts, - self.pre_run_cmds, self.post_run_cmds, - self.run_opts, self.sw_images, - self.sw_build_opts) + self.post_build_opts, self.pre_run_cmds, + self.post_run_cmds, self.run_opts, + self.sw_images, self.sw_build_opts) # Process reseed override and create the build_list build_list_names = [] diff --git a/util/dvsim/Test.py b/util/dvsim/Test.py index dc464e8e39332..d73899d00e352 100644 --- a/util/dvsim/Test.py +++ b/util/dvsim/Test.py @@ -117,15 +117,17 @@ def create_tests(tdicts, sim_cfg): @staticmethod def merge_global_opts(tests, global_pre_build_cmds, global_post_build_cmds, - global_build_opts, global_pre_run_cmds, - global_post_run_cmds, global_run_opts, - global_sw_images, global_sw_build_opts): + global_build_opts, global_post_build_opts, + global_pre_run_cmds, global_post_run_cmds, + global_run_opts, global_sw_images, + global_sw_build_opts): processed_build_modes = set() for test in tests: if test.build_mode.name not in processed_build_modes: test.build_mode.pre_build_cmds.extend(global_pre_build_cmds) test.build_mode.post_build_cmds.extend(global_post_build_cmds) test.build_mode.build_opts.extend(global_build_opts) + test.build_mode.post_build_opts.extend(global_post_build_opts) processed_build_modes.add(test.build_mode.name) test.pre_run_cmds.extend(global_pre_run_cmds) test.post_run_cmds.extend(global_post_run_cmds) diff --git a/util/dvsim/modes.py b/util/dvsim/modes.py index 0b42e7b6ca6c9..a883b15aff7d0 100644 --- a/util/dvsim/modes.py +++ b/util/dvsim/modes.py @@ -241,6 +241,7 @@ def __init__(self, bdict): self.post_build_cmds = [] self.en_build_modes = [] self.build_opts = [] + self.post_build_opts = [] self.build_timeout_mins = None self.pre_run_cmds = [] self.post_run_cmds = [] diff --git a/util/prepare_dvsim_z01x.sh b/util/prepare_dvsim_z01x.sh new file mode 100755 index 0000000000000..8f5c06df11f4a --- /dev/null +++ b/util/prepare_dvsim_z01x.sh @@ -0,0 +1,38 @@ +#!/bin/bash + +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# This script copies proprietary Synopsys Z01X scripts that are located +# in the private https://github.com/lowRISC/opentitan_fi_z01x repository +# into the public OpenTitan repostitory. +# Before starting any Z01X simulations with DVSIM, run this script. +# +# Contact with the email subject: "VC-ZOIX access" +# to request access to the private opentitan_fi_z01x repository. +# +# Usage: +# git clone git@github.com:lowRISC/opentitan_fi_z01x.git +# git clone git@github.com:lowRISC/opentitan.git +# export Z01X_DIR= +# export OT_DIR= +# cd opentitan/ +# ./util/prepare_dvsim_z01x.sh + +if [[ -z "${Z01X_DIR}" ]]; then + echo "Z01X_DIR environment variable not set." >&2 + exit 1 +else + SRC_DIR="${Z01X_DIR}" +fi + +if [[ -z "${OT_DIR}" ]]; then + echo "OT_DIR environment variable not set." >&2 + exit 1 +else + DST_DIR="${OT_DIR}" +fi + +echo "Copying ${SRC_DIR} into ${DST_DIR}" +cp -R $SRC_DIR/hw $DST_DIR/