Use a single ldr to load a large immediate in lieu of multiple movz/movk instructions (facebook#9712)

Summary:

On Arm64, we may need up to 4 movz/movk instructions to load a 64-bit immediate to a GP register, which may contribute to some non-trivial portion in code size. To reduce the code size, this diff puts an immediate in literal pool and emits a single ldr instruction to load from memory.

Differential Revision: D91732849

Author: mcfi

hphp/runtime/vm/jit/vasm-arm.cpp

@@ -209,7 +209,7 @@ bool flagRequired(Vflags flags, StatusFlags flag) {
 struct Vgen {
   explicit Vgen(Venv& env)
     : env(env)
-    , assem(*env.cb)
+    , assem(*env.cb, &env.meta)
     , a(&assem)
     , base(a->frontier())
     , current(env.current)
@@ -622,12 +622,11 @@ void Vgen::handleLiterals(Venv& env) {
     if (pl.width == 32) {
       cb->dword(static_cast<uint32_t>(pl.value));
     } else if (pl.width == 64) {
-      if (pl.smashable) {
-        // Although the region is actually dead, we mark it as live, so that
-        // the relocator can remove the padding.
-        align(*cb, &env.meta, Alignment::QuadWordSmashable, AlignContext::Live);
-        literalAddress = cb->frontier();
-      }
+      // Although the region is actually dead, we mark it as live, so that
+      // the relocator can remove the padding.
+      align(*cb, &env.meta, Alignment::QuadWordSmashable,
+            pl.smashable ? AlignContext::Live : AlignContext::Dead);
+      literalAddress = cb->frontier();
       cb->qword(pl.value);
     } else {
       not_reached();
@@ -799,11 +798,18 @@ void Vgen::emit(const fallthru& /*i*/) {
 
 #define Y(vasm_opc, simd_w, vr_w, gpr_w, imm) \
 void Vgen::emit(const vasm_opc& i) {          \
+  vixl::Label data;                           \
   if (i.d.isSIMD()) {                         \
     emitSimdImmInt(a, static_cast<uint##vr_w##_t>(i.s.simd_w()), i.d);     \
   } else {                                    \
     Vreg##vr_w d = i.d;                       \
-    a->Mov(gpr_w(d), imm);                    \
+    if constexpr(vr_w > 16) {                 \
+      poolLiteral(*env.cb, env.meta, imm, vr_w, false); \
+      a->bind(&data);                         \
+      a->Ldr(gpr_w(d), &data);                \
+    } else {                                  \
+      a->Mov(gpr_w(d), imm);                  \
+    }                                         \
   }                                           \
 }
 
@@ -857,9 +863,13 @@ void Vgen::emit(const mcprep& i) {
 ///////////////////////////////////////////////////////////////////////////////
 
 void Vgen::emit(const call& i) {
+  vixl::Label data;
   if (!i.stackUnaligned) trap_unaligned_stack();
   recordAddressImmediate();
-  a->Mov(rAsm, i.target);
+
+  poolLiteral(*env.cb, env.meta, (uint64_t)i.target, 32, false);
+  a->bind(&data); // This will be remapped during the handleLiterals phase.
+  a->Ldr(rAsm_w, &data);
   a->Blr(rAsm);
   if (i.watch) {
     *i.watch = a->frontier();
@@ -1135,7 +1145,6 @@ void Vgen::emit(const lea& i) {
 
 void Vgen::emit(const leap& i) {
   vixl::Label imm_data;
-  vixl::Label after_data;
 
   // Cannot use simple a->Mov() since such a sequence cannot be
   // adjusted while live following a relocation.
@@ -1147,8 +1156,12 @@ void Vgen::emit(const leap& i) {
 }
 
 void Vgen::emit(const lead& i) {
+  vixl::Label imm_data;
+
   recordAddressImmediate();
-  a->Mov(X(i.d), i.s.get());
+  poolLiteral(*env.cb, env.meta, (uint64_t)i.s.get(), 32, false);
+  a->bind(&imm_data);  // This will be remapped during the handleLiterals phase.
+  a->Ldr(W(i.d), &imm_data);
 }
 
 #define Y(vasm_opc, arm_opc, src_dst, m)                             \

hphp/runtime/vm/jit/vasm-gen-inl.h

@@ -100,6 +100,7 @@ TCA vwrap_impl(CodeBlock& main, CodeBlock& cold, DataBlock& data,
   if (!meta) {
     dummy_meta.addressImmediates.clear();
     dummy_meta.fallthru.reset();
+    dummy_meta.alignments.clear();
   }
   assertx(dummy_meta.empty());
 

hphp/vixl/a64/assembler-a64.cc

@@ -347,8 +347,9 @@ bool MemOperand::IsPostIndex() const {
 
 
 // Assembler
-Assembler::Assembler(HPHP::CodeBlock& cb)
+Assembler::Assembler(HPHP::CodeBlock& cb, HPHP::jit::CGMeta* meta)
     : cb_(cb)
+    , meta_(meta)
     , next_literal_pool_check_(cb.frontier() + kLiteralPoolCheckInterval)
     , literal_pool_monitor_(0) {
   // Assert that this is an LP64 system.

hphp/vixl/a64/assembler-a64.h

@@ -29,6 +29,7 @@
 
 #include "hphp/util/data-block.h"
 #include "hphp/runtime/vm/jit/types.h"
+#include "hphp/runtime/vm/jit/cg-meta.h"
 
 #include "hphp/vixl/globals.h"
 #include "hphp/vixl/utils.h"
@@ -614,7 +615,7 @@ class Literal {
 // Assembler.
 class Assembler {
  public:
-  explicit Assembler(HPHP::CodeBlock& cb);
+  explicit Assembler(HPHP::CodeBlock& cb, HPHP::jit::CGMeta* meta = nullptr);
 
   // The destructor asserts that one of the following is true:
   //  * The Assembler object has not been used.
@@ -646,6 +647,8 @@ class Assembler {
 
   HPHP::CodeBlock& code() const { return cb_; }
 
+  HPHP::jit::CGMeta* meta() const { return meta_; }
+
   HPHP::jit::TCA base() const { return cb_.base(); }
 
   HPHP::jit::TCA frontier() const {
@@ -1679,7 +1682,7 @@ class Assembler {
   }
 
   void CheckLiteralPool(LiteralPoolEmitOption option = JumpRequired);
-  void EmitLiteralPool(LiteralPoolEmitOption option = NoJumpRequired);
+  void EmitLiteralPool(LiteralPoolEmitOption option = JumpRequired);
   size_t LiteralPoolSize();
 
   static bool IsImmLogical(uint64_t value, unsigned width) {
@@ -1860,7 +1863,7 @@ class Assembler {
 
   // The buffer into which code and relocation info are generated.
   HPHP::CodeBlock& cb_;
-
+  HPHP::jit::CGMeta* meta_;
   std::list<Literal*> literals_;
   HPHP::CodeAddress next_literal_pool_check_;
   unsigned literal_pool_monitor_;

hphp/vixl/a64/macro-assembler-a64.cc

@@ -277,26 +277,35 @@ void MacroAssembler::Mov(const Register& rd, uint64_t imm) {
     Register temp = rd.IsSP() ? AppropriateTempFor(rd) : rd;
 
     assert((reg_size % 16) == 0);
-    bool first_mov_done = false;
-    for (unsigned i = 0; i < (reg_size / 16); i++) {
-      uint64_t imm16 = (imm >> (16 * i)) & 0xffffL;
-      if (imm16 != 0) {
-        if (!first_mov_done) {
-          // Move the first non-zero 16-bit chunk into the destination register.
-          movz(temp, imm16, 16 * i);
-          first_mov_done = true;
-        } else {
-          // Construct a wider constant.
-          movk(temp, imm16, 16 * i);
+
+    if (meta() == nullptr) {
+      bool first_mov_done = false;
+      for (unsigned i = 0; i < (reg_size / 16); i++) {
+        uint64_t imm16 = (imm >> (16 * i)) & 0xffffL;
+        if (imm16 != 0) {
+          if (!first_mov_done) {
+            // Move the first non-zero 16-bit chunk into the destination register.
+            movz(temp, imm16, 16 * i);
+            first_mov_done = true;
+          } else {
+            // Construct a wider constant.
+            movk(temp, imm16, 16 * i);
+          }
         }
       }
+      assert(first_mov_done);
+      __builtin_debugtrap();
+    } else {
+      Label data;
+      meta()->addressImmediates.insert(code().frontier());
+      poolLiteral(code(), *meta(), imm, 64, false);
+      bind(&data);
+      Ldr(rd, &data);
     }
 
     if (rd.IsSP()) {
       mov(rd, temp);
     }
-
-    assert(first_mov_done);
   }
 }
 

hphp/vixl/a64/macro-assembler-a64.h

@@ -29,7 +29,6 @@
 #include "hphp/vixl/a64/assembler-a64.h"
 #include "hphp/vixl/a64/debugger-a64.h"
 
-
 #define LS_MACRO_LIST(V)                                      \
   V(Ldrb, Register&, rt, LDRB_w)                              \
   V(Strb, Register&, rt, STRB_w)                              \
@@ -45,8 +44,8 @@ namespace vixl {
 
 class MacroAssembler : public Assembler {
  public:
-  explicit MacroAssembler(HPHP::CodeBlock& cb)
-      : Assembler(cb),
+  explicit MacroAssembler(HPHP::CodeBlock& cb, HPHP::jit::CGMeta* meta = nullptr)
+      : Assembler(cb, meta),
 #ifndef NDEBUG
         allow_macro_instructions_(true),
 #endif