Optimize FPGAs

[numberZero]

A mesecon FPGA performs computation on each input change, which takes CPU time. But, it has only 4-bit input, which is just 16 possible states. Thus its output can be precomputed and stored in the metadata as a 16-byte string (technically only 64 bits are needed but packing into a 8-byte string would be too cumbersome).

Previous attempt: #631.

[FaberUnserzeit]

This is a good idea as long as FPGAs remain as they are, i.e. without the possibility of back-referencing registers in order to create flipflops, which is a change I wanted to propose, because I implemented it for building a computer in minetest by just using logic gates and FPGAs, and it turned out to work well:
https://github.com/FaberUnserzeit/mesecons/blob/master/mesecons_fpga/logic.lua
I built a 256 Byte RAM (with 2048 FPGAs) plus some 8 bit registers and other circuitry, and the performance was still good on an Athlon X3 with 8 GB of RAM. Mesecons FPGAs are fast enough already on my opinion.