🐛 Synthesis of division and modulo operation generates wrong gate sequence

[TooMuchDakka]

Environment information

• OS: Windows 10 x64
• C++ Compiler: clang 17.0.3
• MQT-Core: 3.0.3
• MQT-Syrec: Commit #a95ae75

Description

Simulating the execution of the generated quantum computation for the following two SyReC programs will generate a missmatch between the expected and actual output values:

// IN: 001000 | EXPECTED OUT: 001000 | ACTUAL OUT: 001011
module main(in a(2), in b(2), out c(2)) c ^= (a / b)

// IN: 001000 | EXPECTED OUT: 001000 | ACTUAL OUT: 001010
module main(in a(2), in b(2), out c(2)) c ^= (a % b)

Additionally, it is not clear what the expected output/behaviour of the synthesis algorithms should be when a division by 0/modulo 0 operation is encountered but this could depend on the used synthesis algorithms. In case of the syrec::LineAwareSynthesis and syrec::CostAwareSynthesis algorithms, the output for the two SyReC programs above is the following:

// IN: 000000, OUT: 000011 (a=0, b=0, c=3)
// IN: 100000, OUT: 100011 (a=1, b=0, c=3)
// IN: 010000, OUT: 010011 (a=2, b=0, c=3)
// IN: 110000, OUT: 110011 (a=3, b=0, c=3)
module main(in a(2), in b(2), out c(2)) c ^= (a / b)

// IN: 000000, OUT: 000000 (a=0, b=0, c=0)
// IN: 100000, OUT: 100010 (a=1, b=0, c=1)
// IN: 010000, OUT: 010001 (a=2, b=0, c=2)
// IN: 110000, OUT: 110011 (a=3, b=0, c=3)
module main(in a(2), in b(2), out c(2)) c ^= (a % b)

Expected behavior

The values of the N output qubits used to store the result of the division/modulo operations with the divisor greater than 0 should be equal to the values determined by a conventional devisor/modulo circuit with N-bit input/outputs

How to Reproduce

1. Perform a build from source of mqt.syrec
2. Launch the syrec-editor python application and copy the SyReC circuit from the bug description into the code editor
3. Select either the cost or line aware synthesis radio button and then press the 'Build' button
4. Click on the 'Simulate' button and check the reported input/output pairs