Duplicate synthesis errors during evaluation of VariableAccess on the left-hand side of the assignment in LineAwareSynthesis

[TooMuchDakka]

At the time this issue was written I am using the 2.0.0 (commit c90cc2f) of this project.

When trying to synthesis an assignment whos VariableAccess on the left-hand side contains a synthesis error:

module main(inout a(2))
 for $i = 0 to #a do
  ++= a.$i
 rof

using the LineAwareSynthesis, two duplicate synthesis errors are reported:

User defined bitrange start value '2' was not within the valid range [0, 2] in bitrange access on variable a 
User defined bitrange start value '2' was not within the valid range [0, 2] in bitrange access on variable a 

while when synthesizing the same SyReC module using the CostAwareSynthesis will only report one synthesis error.

The source of this 'error' is that to determine whether an assignment can be handled by the LineAwareSynthesis the latter will evaluate the left-hand side of the to be processed assignment which in our case generates the first synthesis error. With the LineAwareSynthesis having determined that it cannot handle the assignment it delegates its synthesis to the SyrecSynthesis base class which will reevaluate the VariableAccesses of the assignment and thus leading to the second synthesis error.