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ramielkhatibPQSramielkhatibPQS
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Fix PLL timeout value and clear RCC structs
1 parent c4ce324 commit 6da33e1

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4 files changed

+14
-14
lines changed

4 files changed

+14
-14
lines changed

‎stm32f2/stm32f2_hal.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ void platform_init(void)
1717
//HAL_Init();
1818

1919
#if defined(USE_INTERNAL_CLK)
20-
RCC_OscInitTypeDef RCC_OscInitStruct;
20+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
2121
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
2222
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
2323
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -29,15 +29,15 @@ void platform_init(void)
2929
RCC_OscInitStruct.PLL.PLLQ = 7; // divisor for RNG, USB and SDIO
3030
HAL_RCC_OscConfig(&RCC_OscInitStruct);
3131

32-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
32+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
3333
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
3434
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
3535
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
3636
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
3737
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
3838
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_ACR_LATENCY_0WS); // wait states not needed for < 30MHz
3939
#elif defined(USE_PLL)
40-
RCC_OscInitTypeDef RCC_OscInitStruct;
40+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
4141
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
4242
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
4343
RCC_OscInitStruct.HSIState = RCC_HSI_ON; // HSI is needed for the RNG
@@ -51,7 +51,7 @@ void platform_init(void)
5151
for(;;);
5252
}
5353

54-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
54+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
5555
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
5656
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
5757
RCC_ClkInitStruct.AHBCLKDivider = HSE_AHBCLKDIV_HVALUE;
@@ -61,7 +61,7 @@ void platform_init(void)
6161
FLASH->ACR |= 0b111 << 8; //enable ART acceleration
6262

6363
#else
64-
RCC_OscInitTypeDef RCC_OscInitStruct;
64+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
6565
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
6666
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
6767
RCC_OscInitStruct.HSIState = RCC_HSI_ON; // HSI is needed for the RNG
@@ -75,7 +75,7 @@ void platform_init(void)
7575
for(;;);
7676
}
7777

78-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
78+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
7979
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
8080
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
8181
RCC_ClkInitStruct.AHBCLKDivider = HSE_AHBCLKDIV_HVALUE;

‎stm32f2/stm32f2xx_hal_rcc_ex.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
395395
* @brief RCC registers bit address in the alias region
396396
* @{
397397
*/
398-
#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
398+
#define PLL_TIMEOUT_VALUE ((uint32_t)1E6 * 2U) /* 2 ms */
399399
/**
400400
* @}
401401
*/

‎stm32f4/stm32f4_hal.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ void platform_init(void)
3232
#endif
3333

3434
#if defined(USE_INTERNAL_CLK)
35-
RCC_OscInitTypeDef RCC_OscInitStruct;
35+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
3636
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
3737
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
3838
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -44,15 +44,15 @@ void platform_init(void)
4444
RCC_OscInitStruct.PLL.PLLQ = 7; // divisor for RNG, USB and SDIO
4545
HAL_RCC_OscConfig(&RCC_OscInitStruct);
4646

47-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
47+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
4848
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
4949
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
5050
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
5151
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
5252
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
5353
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_ACR_LATENCY_0WS); // wait states not needed for < 30MHz
5454
#elif defined(USE_PLL)
55-
RCC_OscInitTypeDef RCC_OscInitStruct;
55+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
5656
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
5757
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
5858
RCC_OscInitStruct.HSIState = RCC_HSI_ON; // HSI is needed for the RNG
@@ -66,7 +66,7 @@ void platform_init(void)
6666
for(;;);
6767
}
6868

69-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
69+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
7070
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
7171
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
7272
RCC_ClkInitStruct.AHBCLKDivider = HSE_AHBCLKDIV_HVALUE;
@@ -76,7 +76,7 @@ void platform_init(void)
7676
FLASH->ACR |= 0b111 << 8; //enable ART acceleration
7777

7878
#else
79-
RCC_OscInitTypeDef RCC_OscInitStruct;
79+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8080
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
8181
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
8282
RCC_OscInitStruct.HSIState = RCC_HSI_ON; // HSI is needed for the RNG
@@ -90,7 +90,7 @@ void platform_init(void)
9090
for(;;);
9191
}
9292

93-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
93+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
9494
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
9595
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
9696
RCC_ClkInitStruct.AHBCLKDivider = HSE_AHBCLKDIV_HVALUE;

‎stm32f4/stm32f4xx_hal_rcc_ex.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6826,7 +6826,7 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
68266826
#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
68276827
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
68286828

6829-
#define PLL_TIMEOUT_VALUE 1E6 * 2U /* 2 ms */
6829+
#define PLL_TIMEOUT_VALUE ((uint32_t)1E6 * 2U) /* 2 ms */
68306830
/**
68316831
* @}
68326832
*/

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