Big update to PLL programming.

Updates all PLL registers, in the prescribed order, whenever any of them
needs to be updated. Towards fixing
#490.

Functional (but not fully tested) for XIN case; not tested at all with
external clock.

Author: jpcrypt

software/chipwhisperer/capture/scopes/OpenADC.py

@@ -317,7 +317,6 @@ def _default_setup(self):
         self.adc.samples = self.DEFAULT_ADC_SAMPLES
         self.adc.offset = 0
         self.adc.basic_mode = 'rising_edge'
-        self.clock.clkgen_freq = self.DEFAULT_CLOCKGEN_FREQ
         self.trigger.triggers = 'tio4'
         self.io.tio1 = self.io.GPIO_MODE_SERIAL_RX
         self.io.tio2 = self.io.GPIO_MODE_SERIAL_TX
@@ -329,6 +328,7 @@ def _default_setup(self):
             self.clock.clkgen_freq = self.DEFAULT_CLOCKGEN_FREQ
             self.clock.adc_mul = self.DEFAULT_ADC_MUL
         else:
+            self.clock.clkgen_freq = self.DEFAULT_CLOCKGEN_FREQ
             self.clock.adc_src = 'clkgen_x4'
 
     def default_setup(self, verbose=True, sleep=0.2):
@@ -684,7 +684,6 @@ def con(self, sn=None, idProduct=None, bitstream=None, force=False, prog_speed=1
             self.decode_IO = ChipWhispererDecodeTrigger.ChipWhispererDecodeTrigger(self.sc)
 
         if cwtype in ["cwhusky", "cwhusky-plus"]:
-            # self.pll = ChipWhispererHuskyClock.CDCI6214(self.sc)
             self._fpga_clk = ClockSettings(self.sc, hwinfo=self.hwinfo, is_husky=True)
             self.glitch_drp1 = XilinxDRP(self.sc, "CG1_DRP_DATA", "CG1_DRP_ADDR", "CG1_DRP_RESET")
             self.glitch_drp2 = XilinxDRP(self.sc, "CG2_DRP_DATA", "CG2_DRP_ADDR", "CG2_DRP_RESET")