Husky: improper reset when reconnecting to a Husky that has a high ADC clock frequency.

[jpcrypt]

When connecting to a Husky that was:

1. previously connected (since being powered up) and
2. had an ADC sampling clock greater than ~150 MHz

power sample collection and storage may not work correctly.

Examples of this scenario include:

• running a Jupyter notebook, restarting its kernel, then running the same notebook (or a different one) without powering down Husky
• running a Python script, then running the same script or a different one without powering down Husky
• calling scope.dis() followed by scope.con() or scope = cw.scope() in the same notebook

This problem can manifest itself in traces that look very badly aligned, like this:

instead of properly aligned, like this:

scope.adc_test() can also be seen to fail.

The issue lies with improper resetting of FPGA logic when the ADC clock is high.
Running this after connecting to the scope object appears to resolve the issue:

scope.fpga_reg_write('RESET', [1])
scope.fpga_reg_write('RESET', [0])

Alternatively, setting the ADC clock to its default (e.g. via scope.default_setup()) before disconnecting the scope should also avoid the issue.