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tests: drivers: Test SPIM with Clock Control active
Test nrf54h slow SPIM the Clock Control is active and used Signed-off-by: Bartosz Miller <[email protected]>
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‎tests/drivers/spi/spim_clock_control/CMakeLists.txt‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(spim_clock_control)
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target_sources(app PRIVATE src/main.c)

‎tests/drivers/spi/spim_clock_control/boards/nrf54h20dk_nrf54h20_cpuapp.overlay‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/* Required loopbacks:
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* P0.07 <-> P0.06
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*/
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&pinctrl {
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dut_spi_default: dut_spi_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
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<NRF_PSEL(SPIM_MOSI, 0, 7)>,
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<NRF_PSEL(SPIM_MISO, 0, 6)>;
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};
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};
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dut_spi_sleep: dut_spi_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
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<NRF_PSEL(SPIM_MISO, 0, 6)>,
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<NRF_PSEL(SPIM_MOSI, 0, 7)>;
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low-power-enable;
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};
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};
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};
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dut_spi: &spi130 {
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compatible = "nordic,nrf-spim";
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status = "okay";
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pinctrl-0 = <&dut_spi_default>;
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pinctrl-1 = <&dut_spi_sleep>;
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pinctrl-names = "default", "sleep";
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overrun-character = <0x00>;
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memory-regions = <&cpuapp_dma_region>;
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cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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zephyr,pm-device-runtime-auto;
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dut_spi_dt: test-spi-dev@0 {
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compatible = "vnd,spi-device";
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reg = <0>;
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spi-max-frequency = <DT_FREQ_M(1)>;
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};
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};
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&fll16m {
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status = "okay";
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};
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&exmif {
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status = "disabled";
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};

‎tests/drivers/spi/spim_clock_control/prj.conf‎

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CONFIG_SPI=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_ZTEST=y

‎tests/drivers/spi/spim_clock_control/src/main.c‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/linker/devicetree_regions.h>
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#include <zephyr/devicetree/clocks.h>
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#include <zephyr/drivers/clock_control/nrf_clock_control.h>
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#include <zephyr/ztest.h>
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/* SPI MODE 0 */
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#define SPI_MODE (SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_LINES_SINGLE | SPI_TRANSFER_MSB)
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#define DUT_SPI_NODE DT_NODELABEL(dut_spi)
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#define TEST_BUFFER_SIZE 512
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#define REQUEST_SERVING_WAIT_TIME_US 10000
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static struct spi_dt_spec spim_spec = SPI_DT_SPEC_GET(DT_NODELABEL(dut_spi_dt), SPI_MODE, 0);
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const struct device *const fll16m_dev = DEVICE_DT_GET(DT_NODELABEL(fll16m));
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#define MEMORY_SECTION(node) \
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COND_CODE_1(DT_NODE_HAS_PROP(node, memory_regions), \
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(__attribute__((__section__( \
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LINKER_DT_NODE_REGION_NAME(DT_PHANDLE(node, memory_regions)))))), \
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())
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static uint8_t tx_buffer[TEST_BUFFER_SIZE] MEMORY_SECTION(DT_BUS(DT_NODELABEL(dut_spi_dt)));
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static uint8_t rx_buffer[TEST_BUFFER_SIZE] MEMORY_SECTION(DT_BUS(DT_NODELABEL(dut_spi_dt)));
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const struct nrf_clock_spec fll16m_open_loop_mode = {
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.frequency = MHZ(16),
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.accuracy = NRF_CLOCK_CONTROL_ACCURACY_PPM(20000),
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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};
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const struct nrf_clock_spec fll16m_bypass_mode = {
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.frequency = MHZ(16),
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.accuracy = NRF_CLOCK_CONTROL_ACCURACY_PPM(30),
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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};
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static void request_clock_spec(const struct device *clk_dev, const struct nrf_clock_spec *clk_spec)
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{
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int ret = 0;
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int res = 0;
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struct onoff_client cli;
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uint32_t rate;
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TC_PRINT("Clock: %s, requesting frequency=%d, accuracy=%d, precision=%d\n", clk_dev->name,
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clk_spec->frequency, clk_spec->accuracy, clk_spec->precision);
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sys_notify_init_spinwait(&cli.notify);
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ret = nrf_clock_control_request(clk_dev, clk_spec, &cli);
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zassert_true((ret >= 0 && ret <= 2),
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"Clock control request response outside of range, ret = %d\n", ret);
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do {
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ret = sys_notify_fetch_result(&cli.notify, &res);
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k_yield();
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} while (ret == -EAGAIN);
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zassert_ok(ret, "ret != 0, ret = %d\n", ret);
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zassert_ok(res, "ret != 0, ret = %d\n", res);
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ret = clock_control_get_rate(clk_dev, NULL, &rate);
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if (ret != -ENOSYS) {
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zassert_ok(ret, "ret != 0, ret = %d\n", ret);
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zassert_equal(rate, clk_spec->frequency,
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"Clock frequency != requested frequnecy\n");
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k_busy_wait(REQUEST_SERVING_WAIT_TIME_US);
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}
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}
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static void *test_setup(void)
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{
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zassert_true(spi_is_ready_dt(&spim_spec), "SPIM device is not ready");
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return NULL;
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}
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static void set_buffers(void)
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{
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memset(tx_buffer, 0x8B, TEST_BUFFER_SIZE);
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memset(rx_buffer, 0xFF, TEST_BUFFER_SIZE);
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}
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static void test_spim_with_clock_control(void)
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{
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int err;
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struct spi_buf tx_spi_buf = {.buf = tx_buffer, .len = TEST_BUFFER_SIZE};
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struct spi_buf_set tx_spi_buf_set = {.buffers = &tx_spi_buf, .count = 1};
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struct spi_buf rx_spi_buf = {.buf = rx_buffer, .len = TEST_BUFFER_SIZE};
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struct spi_buf_set rx_spi_buf_set = {.buffers = &rx_spi_buf, .count = 1};
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set_buffers();
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err = spi_transceive_dt(&spim_spec, &tx_spi_buf_set, &rx_spi_buf_set);
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zassert_ok(err, "SPI transceive failed: %d\n", err);
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zassert_mem_equal(tx_buffer, rx_buffer, TEST_BUFFER_SIZE, "TX buffer != RX buffer\n");
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}
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ZTEST(spim_clock_control, test_spim_with_clock_control_active_fll16m_open_loop)
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{
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request_clock_spec(fll16m_dev, &fll16m_open_loop_mode);
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test_spim_with_clock_control();
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}
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ZTEST(spim_clock_control, test_spim_with_clock_control_active_fll16m_bypass)
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{
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request_clock_spec(fll16m_dev, &fll16m_bypass_mode);
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test_spim_with_clock_control();
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}
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ZTEST_SUITE(spim_clock_control, NULL, test_setup, NULL, NULL, NULL);

‎tests/drivers/spi/spim_clock_control/testcase.yaml‎

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common:
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sysbuild: true
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depends_on: gpio
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harness: ztest
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tags:
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- drivers
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- spim
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- ci_tests_drivers_spi
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tests:
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drivers.spim_clock_control:
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platform_allow:
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf54h20dk/nrf54h20/cpuapp
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harness_config:
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fixture: gpio_loopback

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