Make mtime frequency configurable

Author: object-Object

README.md

@@ -43,7 +43,7 @@ Addresses `0xf0000000` - `0xffffffff` are reserved for system purposes such as M
 
 ### Machine Timers
 
-The `mtime` and `mtimecmp` registers are mapped to `0xf0000000` and `0xf0000008` respectively, and have a period of 1 μs. The timer registers are not accessible to privilege modes lower than M-mode.
+The `mtime` and `mtimecmp` registers are mapped to `0xf0000000` and `0xf0000008` respectively. The frequency is configurable, defaulting to a period of 1 μs. The timer registers are not accessible to privilege modes lower than M-mode.
 
 ### UART
 
@@ -149,10 +149,6 @@ CSR values are stored either in a RAM processor (CSRS), in a variable in the CPU
 
 The `[m]cycle[h]` counter is incremented at the start of each worker's tick, just before it jumps back into code execution. The period should be something like `number of workers * 1/60 seconds`, but it will vary based on FPS.
 
-### `time`
-
-The `[m]time[h]` counter is based on the `@time` value in Mindustry. It has a period of 1 μs, and is incremented once per tick by the controller based on the time delta since the previous tick.
-
 ## riscv-arch-test
 
 mlogv32 currently passes all compliance tests for the `RV32IMASUZicsr_Zifencei` ISA.

linux/buildroot/board/mlogv32/dts/mlogv32.dtb

@@ -41,7 +41,7 @@
     cpus {
         #address-cells = <1>;
         #size-cells = <0>;
-        timebase-frequency = <1000000>;
+        timebase-frequency = <1000>;
 
         cpu@0 {
             device_type = "cpu";

linux/buildroot/board/mlogv32/dts/mlogv32.dts

@@ -19,7 +19,7 @@
 #include <sbi_utils/serial/xlnx_uartlite.h>
 #include <sbi_utils/timer/aclint_mtimer.h>
 
-#define MLOGV32_MTIME_FREQ		1000000
+#define MLOGV32_MTIME_FREQ		1000
 #define MLOGV32_MTIME_ADDR		0xf0000000
 #define MLOGV32_MTIME_SIZE		0x8
 #define MLOGV32_MTIMECMP_ADDR		0xf0000008

linux/buildroot/opensbi/platform/mlogv32/platform.c

@@ -24,6 +24,8 @@
 
     set UART_FIFO_CAPACITY {{# UART_FIFO_CAPACITY }}  # UART TX/RX FIFO capacity in bytes (max 253)
 
+    set MTIME_FREQUENCY {{# MTIME_FREQUENCY }} # mtime frequency in Hz (eg. 1000 -> ms, 1000000 -> μs)
+
     # computed values
 #%+ set RAM_START = '0x80000000'
 
@@ -49,6 +51,8 @@ done_icache:
 
     op add UART_FIFO_MODULO UART_FIFO_CAPACITY 1  # actual number of indices used for each FIFO, keeping one empty to check if the buffer is full (max 254)
 
+    op div MTIME_SCALE MTIME_FREQUENCY 1000 # mtime multiplier from @time (eg. 1 -> ms, 1000 -> μs)
+
     stop
 
 #%- if false
@@ -60,6 +64,7 @@ set _ MEMORY_WIDTH
 set _ ROM_SIZE
 set _ PROGRAM_ROM_ICACHE_SIZE
 set _ UART_FIFO_MODULO
+set _ MTIME_SCALE
 set _ MEMORY_X
 set _ MEMORY_Y
 # {% endraw %}

src/config/base.mlog.jinja

@@ -7,6 +7,7 @@ template: base.mlog.jinja
 defaults:
   UART_FIFO_CAPACITY: 253
   DATA_ROM_ROWS: 0
+  MTIME_FREQUENCY: 1_000_000
 
 configs:
   riscv-arch-test:
@@ -42,3 +43,4 @@ configs:
     DATA_ROM_ROWS: 14
     RAM_ROWS: 14
     ICACHE_ROWS: 14
+    MTIME_FREQUENCY: 1000

src/config/configs.yaml

@@ -45,6 +45,7 @@ reset:
     read RAM_END {{CONFIG}} "RAM_END"
     read ICACHE_END {{CONFIG}} "ICACHE_END"
     read UART_FIFO_MODULO {{CONFIG}} "UART_FIFO_MODULO"
+    read MTIME_SCALE {{CONFIG}} "MTIME_SCALE"
 
     op idiv RAM_START_PROC ROM_SIZE {{ROM_PROC_BYTES}}
 
@@ -296,14 +297,14 @@ end_breakpoint:
     # update mtime
     # TODO: handle mtimeh overflow
 
-    op sub delta_ms @time last_mtime_update
-    op mul delta_ms delta_ms 1000 # ms -> μs
+    op sub _delta @time last_mtime_update
+    op mul _delta _delta MTIME_SCALE
 
-    op add csr_mtime csr_mtime delta_ms
+    op add csr_mtime csr_mtime _delta
     op floor csr_mtime csr_mtime
 
-    op shr overflow csr_mtime 32
-    op add csr_mtimeh csr_mtimeh overflow
+    op shr _overflow csr_mtime 32
+    op add csr_mtimeh csr_mtimeh _overflow
 
     op mod csr_mtime csr_mtime 0x100000000
 

src/cpu/controller.mlog.jinja

@@ -220,6 +220,9 @@ loop:
 
     read UART_FIFO_MODULO {{CPU}} "UART_FIFO_MODULO"
 
+    read MTIME_SCALE {{CPU}} "MTIME_SCALE"
+    op mul MTIME_FREQUENCY MTIME_SCALE 1000
+
     read uart_flags {{CPU}} "uart_flags"
 
     set addr1 ""
@@ -614,11 +617,17 @@ loop__no_mark_icache:
 
     print "{{ '{0}\\n' * 5 }}"
 
-    format mtimecmp
+    set n mtimecmp
+    op add ret @counter 1
+    jump format_time always
 
-    format stimecmp
+    set n stimecmp
+    op add ret @counter 1
+    jump format_time always
 
-    format mtime
+    set n mtime
+    op add ret @counter 1
+    jump format_time always
 
     format mcycle
 
@@ -981,6 +990,18 @@ format_privilege_mode:
     format "reserved"; set @counter ret
     format "machine"; set @counter ret
 
+format_time:
+    jump format_unknown equal n -1
+
+    op mod _rem n MTIME_FREQUENCY
+    op idiv n n MTIME_FREQUENCY
+    jump format_unknown equal _rem 0
+
+    format "{0}.{0}"
+    format n
+    format _rem
+    set @counter ret
+
 # creates a marker on the ram proc containing a given address
 # the caller should print a format string with a placeholder for the address
 # address ->