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    • a2o

      Public
      The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
      Verilog
      1051111Updated May 16, 2025May 16, 2025
    • toy-sram

      Public
      High-specific-bandwidth memory design
      Verilog
      2810Updated Jul 31, 2023Jul 31, 2023
    • 0000Updated Jun 22, 2023Jun 22, 2023
    • power-fv

      Public
      POWER-FV - Mirrored from OPF Git
      Python
      2200Updated May 31, 2023May 31, 2023
    • OpenPower Verification
      Verilog
      2800Updated Feb 22, 2023Feb 22, 2023
    • eFabless MPW-7
      Verilog
      1000Updated Feb 20, 2023Feb 20, 2023
    • a2p-mpw

      Public
      0000Updated Feb 17, 2023Feb 17, 2023
    • a2p

      Public
      Verilog
      5800Updated Aug 29, 2022Aug 29, 2022
    • a2i

      Public
      The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
      VHDL
      24710Updated Aug 12, 2022Aug 12, 2022
    • ac922interposer

      Public
      AC922 Interposer Board for DC-SCM BMC - mirrored from OPF git - Maintained by the LibreBMC SIG
      XSLT
      2300Updated Aug 10, 2022Aug 10, 2022
    • openpower

      Public
      OpenPOWER Foundation General Information & Repository Listing
      32300Updated Mar 28, 2022Mar 28, 2022
    • LPC Peripheral Repository mirrored to OPF Git https://git.openpower.foundation/librebmc/lpcperipheral
      Python
      5400Updated Feb 3, 2022Feb 3, 2022