Demodulation via Linien python script | understanding program output #280
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I am not exactly sure what the issue is. What you describe seems to make sense to me, I think you can calculate the phase difference on your client computer. As for the scaling, have a look at Note that streaming the data continuously is currently not possible. If you want to calculate the phase difference on the FPGA you would have to modify the gateware. In that case it might be best to fork Linien and modify it there. I do not think that this functionality is within the scope of Linien. Happy to port things back if there is anything of use to a larger user base. As for modifying the gateware, migen-tutorial might be useful as a quick start. Also have a look at https://github.com/linien-org/linien/wiki/Development for setting up your environment. Also, you might want to have a look at pyrpl: they do have functionality for IQ demodulation that might be more suitable for what you want to do: https://pyrpl.readthedocs.io/en/latest/_modules/pyrpl/hardware_modules/iq.html |
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Hi! I would like to utilize the IQ demodulation capability to apply to an input signal. I aim to compute the phase difference between incoming and reference signals of the same frequencies.
To this end, I figured I could use the IQ demodulation of an IN1 input signal on the Red Pitaya using Linien. This is because the parameters class exposes the in-phase and quadrature signals ('error_signal_1' and 'error_signal_1_quadrature'). I think I'm yet to figure out how to know the actual phase differences. I think I first need to lock my reference to the incoming signal and consequently measure the phase difference from there on (if someone could throw some advice here, I'd be grateful).
Following the 'to_plot' object it appears to me that the data type is int16. What is the conversion factor to the voltage scale? My input to IN1 channel is a sinusoid of frequency 1 kHz (fluctuates) and amplitude 1V from a signal generator. How do I adjust the amplitude of my demodulation IQ signals so as to match the incoming signal amplitude? The plot of in-phase and quadrature signals is attached. Also, the Linien appears to grab 2048 samples in a capture window. How do I know the time scale (seconds) and the sampling rate used on the FPGA ADC?
Next, I would need to apply a low pass filter across each of the channels and observe the DC values that represent the phases (phase difference by arctan operation). Is it feasible to apply IIR filters of Linien for each of the desired signals?
Please advise!
c = LinienClient(...)
c.parameters.modulation_frequency.value = 0.001 * MHz
c.parameters.sweep_speed.value = 7
c.parameters.lock.value = False
c.parameters.dual_channel.value = False
c.parameters.fast_mode.value = False
c.parameters.demodulation_multiplier_a.value = 1
c.parameters.demodulation_phase_a.value = 0
c.connection.root.write_registers()
plot_data = pickle.loads(c.parameters.to_plot.value)
error_signal = plot_data["error_signal_1"]
error_signal_q = plot_data["error_signal_1_quadrature"]
plt.plot(error_signal)
plt.plot(error_signal_q)
plt.show()
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