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Description
As reported in various places in chat. Since the FPGA handles the Tofino sequencing and can survive SP reset, we've had bugs in the past where the SP and FPGA get out of sync with one another and do not recover properly. We expect that may have been the case here somehow but could not verify that since the production images don't have udprpc
, rendering hiffy
unusable in this context.
I've flashed the v1.0.37
dev image on this switch (which has udprpc
) so we can debug further if it reproduces.
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