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PCFX: Controller port edge-case investigations #164

@dshadoff

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@dshadoff

1) When controller scan in in progress (~100usec in length), bit 0 (value 1) is high, and bit 3 (value 8) is low.

Current expectation is that these transition simultaneously (i.e. "value 1 -> value 8", not "1 -> 0 -> 8", and not "1 ->9 -> 8").

This needs to be confiirmed on an actual machine. If there is a transitional value, it would be held only for a brief moment which may be difficult to witness, so current implementation is an adequate representation.

2) Mednafen does not appear to have full-word read/write io-handler implementations for controller ports.

It is not clear whether these operations take place as (multiple) implicit halfword-read/writes, or whether they produce bad results.

Needs to be investigated.

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