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I went in to all a slice row kernel in sams, but found that `sams`
didn't update state_alpha and `fast` didn't update anything but the row
and column reassignment. Fixed.
Copy file name to clipboardExpand all lines: CHANGELOG.md
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@@ -12,6 +12,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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### Fixed
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- Initializing an engine with a codebook that has a different number of rows than the data will result in an error instead of printing a bunch on nonsense.
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- Pylace default transition sets didn't hit all required transitions
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