Add support for Sipeed Tang 9k

[RichardPar]

Hi there,

I recently got one of the above toys.. adding the project to the Gowin FPGA Designer 1.9.8.10 and changing the target, there are many errors abound. (Complains about Verilig versions and syntax) and in the end it doesnt syntheise.

ERROR (PA2024) : The number(335) of ports exceeds the resource limit 59 regular I/Os and 1 RECONFIG_N I/Os of current device, you can also use 4 JTAG, 3 SSPI and 4 MSPI I/Os by configuring Dual-Purpose Pin as regular I/Os.

its clearly on some or other whacky trip :D Loading the project and not changing anything results in errors..

Any pointers would be appriciated..

[pthalin]

Please check that your project settings are correct.

If you change the target you must also update the PLL type and pin mapping.

[krisdover]

@RichardPar did you manage to get this working on your board? I've followed @pthalin's instructions and setup my GOWIN EDA to build this project and program my Tang Nano 4K, but I'm getting corrupted bcdcounts (i.e. time measures) outputted to the screen. I've done some debugging and verified it's definitely not the char_rom.v module. My only guess is that maybe its something to do with the FIFO_HS_Top IPC and the cross clock domains?

[pthalin]

I seen this too when using a new gowin ide verson. What version did you use?

[RichardPar]

I didnt ... I just re-wrote something that suited my purposes... seemed less effort as the clocks between the chips are quite different. Richard

…

On Wed, 19 Jul 2023 at 10:55, Kris Dover ***@***.***> wrote: @RichardPar <https://github.com/RichardPar> did you manage to get this working on your board? I've followed @pthalin <https://github.com/pthalin>'s instructions and setup my GOWIN EDA to build this project and program my Tang Nano 4K, but I'm getting corrupted bcdcounts (i.e. time measures) outputted to the screen. I've done some debugging and verified it's definitely not the char_rom.v module. My only guess is that maybe its something to do with the FIFO_HS_Top IPC and the cross clock domains? [image: IMG_20230717_104833] <https://user-images.githubusercontent.com/16514442/254536842-2207c378-10cf-4d82-9236-688c8dd86415.jpg> — Reply to this email directly, view it on GitHub <#3 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAI234NRWH74PKCMQYNL5SDXQ6VHVANCNFSM6AAAAAAVHJKBUM> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[krisdover]

I seen this too when using a new gowin ide verson. What version did you use?
Interesting! I've got a board using the GW1NSR-LV4C FPGA:

Btw, thanks for the awesome work porting time-sleuth to this very affordable development board. It's been fun learning Verilog using this project. 👍

[pthalin]

@krisdover @RichardPar
I can confirm that I get the "corrupted bcdcounts" with Gowin IDE 1.9.8.11 Edu but it works with 1.9.8.7 Edu and 1.9.8.9 Edu. I'm struggling to solve this so please let me know if you find the cause of this.

[krisdover]

Thanks for that update @pthalin. Any idea as to where I can find Gowin IDE 1.9.8.7 Edu? The GOWIN website only has the new 1.9.8.11 Edu version available for download.

I'm struggling to solve this so please let me know if you find the cause of this.

I thought it might be due incompatibilities between the FIFO_HS IP CORE module you stored in the project and new GOWIN EDA toolchain. I've even regenerated the FIFO_HS module in the new v1.9.8.11 EDA and noted that it uses a new encryption version:

Unfortunately I still get the corruption even with the new module.

[krisdover]

@pthalin I just thought I'd share that I've still been playing with code try getting it to work on my Tang 4k and noticed that it would randomly work sometimes, just by chance, when I added or remove some extra registers. So I started to wonder whether these FPGA boards were suffering from some kind of instability, and sure enough I was able to find a few reports online which seem to suggest that it depends on the percentage of FF/LUTs in use:

https://www.reddit.com/r/GowinFPGA/comments/101p9yd/sipeed_tang_nano_4k_9k_gowin_fpgas_become/
YosysHQ/apicula#169