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Merge pull request #1600 from 0xMirasio/master
PPC debugger XML support
2 parents 83c6fb9 + 08650be commit fe462b8

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4 files changed

+72
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lines changed

‎qiling/debugger/gdb/gdb.py‎

Lines changed: 3 additions & 1 deletion
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@@ -183,6 +183,7 @@ def handle_qmark(subcmd: str) -> Reply:
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from unicorn.arm_const import UC_ARM_REG_R11
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from unicorn.arm64_const import UC_ARM64_REG_X29
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from unicorn.mips_const import UC_MIPS_REG_INVALID
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from unicorn.ppc_const import UC_PPC_REG_31
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arch_uc_bp = {
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QL_ARCH.X86 : UC_X86_REG_EBP,
@@ -191,7 +192,8 @@ def handle_qmark(subcmd: str) -> Reply:
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QL_ARCH.ARM64 : UC_ARM64_REG_X29,
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QL_ARCH.MIPS : UC_MIPS_REG_INVALID, # skipped
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QL_ARCH.A8086 : UC_X86_REG_EBP,
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QL_ARCH.CORTEX_M : UC_ARM_REG_R11
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QL_ARCH.CORTEX_M : UC_ARM_REG_R11,
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QL_ARCH.PPC : UC_PPC_REG_31
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}[self.ql.arch.type]
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def __get_reg_idx(ucreg: int) -> int:

‎qiling/debugger/gdb/xml/ppc/ppc-core.xml‎

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@@ -0,0 +1,51 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2007-2020 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.power.core">
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<reg name="r0" bitsize="32" type="uint32"/>
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<reg name="r1" bitsize="32" type="uint32"/>
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<reg name="r2" bitsize="32" type="uint32"/>
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<reg name="r3" bitsize="32" type="uint32"/>
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<reg name="r4" bitsize="32" type="uint32"/>
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<reg name="r5" bitsize="32" type="uint32"/>
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<reg name="r6" bitsize="32" type="uint32"/>
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<reg name="r7" bitsize="32" type="uint32"/>
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<reg name="r8" bitsize="32" type="uint32"/>
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<reg name="r9" bitsize="32" type="uint32"/>
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<reg name="r10" bitsize="32" type="uint32"/>
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<reg name="r11" bitsize="32" type="uint32"/>
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<reg name="r12" bitsize="32" type="uint32"/>
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<reg name="r13" bitsize="32" type="uint32"/>
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<reg name="r14" bitsize="32" type="uint32"/>
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<reg name="r15" bitsize="32" type="uint32"/>
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<reg name="r16" bitsize="32" type="uint32"/>
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<reg name="r17" bitsize="32" type="uint32"/>
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<reg name="r18" bitsize="32" type="uint32"/>
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<reg name="r19" bitsize="32" type="uint32"/>
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<reg name="r20" bitsize="32" type="uint32"/>
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<reg name="r21" bitsize="32" type="uint32"/>
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<reg name="r22" bitsize="32" type="uint32"/>
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<reg name="r23" bitsize="32" type="uint32"/>
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<reg name="r24" bitsize="32" type="uint32"/>
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<reg name="r25" bitsize="32" type="uint32"/>
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<reg name="r26" bitsize="32" type="uint32"/>
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<reg name="r27" bitsize="32" type="uint32"/>
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<reg name="r28" bitsize="32" type="uint32"/>
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<reg name="r29" bitsize="32" type="uint32"/>
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<reg name="r30" bitsize="32" type="uint32"/>
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<reg name="r31" bitsize="32" type="uint32"/>
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<reg name="cr" bitsize="32" type="uint32"/>
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<reg name="lr" bitsize="32" type="code_ptr"/>
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<reg name="pc" bitsize="32" type="code_ptr"/>
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<reg name="msr" bitsize="32" type="uint32"/>
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<reg name="ctr" bitsize="32" type="uint32"/>
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<reg name="xer" bitsize="32" type="uint32"/>
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</feature>

‎qiling/debugger/gdb/xml/ppc/target.xml‎

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@@ -0,0 +1,12 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.
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*!Copying and distribution of this file, with or without modification,
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*!are permitted in any medium without royalty provided the copyright
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*!notice and this notice are preserved. -->
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target xmlns:xi="http://www.w3.org/2001/XInclude">
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<architecture>powerpc:common</architecture>
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<xi:include href="ppc-core.xml"/>
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</target>

‎qiling/debugger/gdb/xmlregs.py‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,10 @@
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reg_map_ymm as x86_regs_ymm
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)
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from qiling.arch.ppc_const import (
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reg_map as ppc_regs
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)
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4145
from qiling.const import QL_ARCH, QL_OS
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RegEntry = Tuple[Optional[int], int, int]
@@ -142,7 +146,8 @@ def __load_regsmap(archtype: QL_ARCH, xmltree: ElementTree.ElementTree) -> Seque
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QL_ARCH.ARM: dict(**arm_regs, **arm_regs_vfp, **arm_regs_q, **arm_regs_s),
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QL_ARCH.CORTEX_M: dict(**cortex_m_regs),
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QL_ARCH.ARM64: dict(**arm64_regs, **arm64_regs_v, **arm64_reg_map_fp),
145-
QL_ARCH.MIPS: dict(**mips_regs_gpr)
149+
QL_ARCH.MIPS: dict(**mips_regs_gpr),
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QL_ARCH.PPC: dict(**ppc_regs)
146151
}[archtype]
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regsinfo = sorted(QlGdbFeatures.__walk_xml_regs(xmltree))

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