Interchange to Bookshelf converter doesn't properly handle bussed nets

[clavin-xlnx]

When trying to convert a much larger design, I encountered this error:

Traceback (most recent call last):
  File "IFsupport/IF2bookshelf.py", line 586, in <module>
    if_parser = IF2bookshelf(bookshelf_dir, args.netlist)
  File "IFsupport/IF2bookshelf.py", line 38, in __init__
    self.netlist_obj = LogicalNetlist(schema_dir, netlist_file)
  File "IFsupport/IF2bookshelf.py", line 500, in __init__
    port_idx = port_bus2idx[port_name].index(port_inst.busIdx.idx)
ValueError: 0 is not in list

I have attached a trivial design example that triggers the bug.
example.zip

To reproduce:

wget https://github.com/rachelselinar/DREAMPlaceFPGA/files/11761406/example.zip
unzip example.zip
python IFsupport/IF2bookshelf.py --netlist example.netlist

Here is what the example looks like in Vivado:

CC: @zhilix

[zhilix]

Hi Chris, I created a PR for this, please take a look.
#17

[clavin-xlnx]

Hi Chris, I created a PR for this, please take a look. #17

This solved the issue for the example provided, but there is more fundamental problem related to creating a map of ports for all cells. It doesn't work when two cells in a design have the same name. I think it might be wise to eliminate these maps and simply look up the information directly. I have updated the example to reproduce the issue:

wget https://github.com/rachelselinar/DREAMPlaceFPGA/files/11841259/example2.zip
unzip example2.zip
python IFsupport/IF2bookshelf.py --netlist example2.netlist

example2.zip

[zhilix]

Hi Chris, I deleted those port maps and updated the IF2bookshelf.py, Please take a look at #19