KeyError placing design with RAMB18

[eddieh-xlnx]

The attached Interchange netlist is a Yosys compilation of the picorv32 design with LUTRAMs disabled, which causes it to use block RAMs instead.

picorv32_ramb18.zip

Running this with the interchange_cut1 branch (currently 4696a20) results in:

$ bin/dreamplacefpga -interchange_netlist picorv32_ramb18.netlist -interchange_device xcvu3p.device -result_dir .
[INFO   ] DREAMPlaceFPGA - Parameters[1] = [{'scl_file': '', 'instance_file': '', 'pin_file': '', 'net_file': '', 'routing_file': '', 'util_file': '', 'pickle_file': '', 'load_pickle': 0, 'aux_input': '', 'gpu': 0, 'num_bins_x': 512, 'num_bins_y': 512, 'global_place_stages': [{'num_bins_x': 512, 'num_bins_y': 512, 'iteration': 2000, 'learning_rate': 0.01, 'wirelength': 'weighted_average', 'optimizer': 'nesterov'}], 'target_density': 1.0, 'density_weight': 8e-05, 'random_seed': 1000, 'result_dir': '.', 'scale_factor': 1.0, 'ignore_net_degree': 3000, 'gp_noise_ratio': 0.025, 'enable_fillers': 1, 'global_place_flag': 1, 'legalize_flag': 1, 'stop_overflow': 0.1, 'dtype': 'float32', 'detailed_place_engine': '', 'detailed_place_command': '-nolegal -nodetail', 'plot_flag': 0, 'RePlAce_ref_hpwl': 350000, 'RePlAce_LOWER_PCOF': 0.95, 'RePlAce_UPPER_PCOF': 1.05, 'gamma': 5.0, 'random_center_init_flag': 1, 'sort_nets_by_degree': 0, 'num_threads': 8, 'dump_global_place_solution_flag': 0, 'dump_legalize_solution_flag': 0, 'routability_opt_flag': 0, 'route_num_bins_x': 512, 'route_num_bins_y': 512, 'node_area_adjust_overflow': 0.15, 'max_num_area_adjust': 3, 'adjust_resource_area_flag': 1, 'adjust_route_area_flag': 1, 'adjust_pin_area_flag': 1, 'area_adjust_stop_ratio': 0.01, 'route_area_adjust_stop_ratio': 0.01, 'pin_area_adjust_stop_ratio': 0.05, 'unit_horizontal_capacity': 209, 'unit_vertical_capacity': 239, 'unit_pin_capacity': 50, 'max_route_opt_adjust_rate': 2.0, 'route_opt_adjust_exponent': 2.0, 'pin_stretch_ratio': 1.414213562, 'max_pin_opt_adjust_rate': 1.5, 'ffPinWeight': 3.0, 'deterministic_flag': 1, 'enable_if': 1, 'enable_site_routing': 0, 'io_pl': '', 'timing_driven_flag': 0, 'timing_iteration_overflow': 0.15, 'max_num_timing_iteration': 20, 'timing_interval': 5, 'criticality_exponent': 9.0, 'beta_ratio': 1.1, 'inflation_ratio': 1.0, 'enableTimingPreclustering': 0, 'lg_alpha': 0.2, 'lg_beta': 0.1, 'write_tcl_flag': 0, 'write_io_placement_flag': 0, 'interchange_netlist': 'picorv32_ramb18.netlist', 'interchange_device': 'xcvu3p.device', 'detailed_place_flag': 0}]
Parsing device file xcvu3p.device
Parsing netlist file picorv32_ramb18.netlist
[WARNING] Net GND_NET connects to instance picorv32_core.cpuregs.0.0 pin WEA[2]. However pin WEA[2] is not listed in .lib as a valid pin for instance type RAMB18E1. FIX
[WARNING] Net GND_NET connects to instance picorv32_core.cpuregs.0.0 pin WEA[3]. However pin WEA[3] is not listed in .lib as a valid pin for instance type RAMB18E1. FIX
[WARNING] Net GND_NET connects to instance picorv32_core.cpuregs.1.0 pin WEA[2]. However pin WEA[2] is not listed in .lib as a valid pin for instance type RAMB18E1. FIX
[WARNING] Net GND_NET connects to instance picorv32_core.cpuregs.1.0 pin WEA[3]. However pin WEA[3] is not listed in .lib as a valid pin for instance type RAMB18E1. FIX
[INFO   ] DREAMPlaceFPGA - Region: 0 #movable_nodes =     1618 movable_node_area =     158.0, placeable_area =   50700.0, filler_node_area =   50542.0, #fillers =  404335, filler sizes =0.3536x0.353553

[INFO   ] DREAMPlaceFPGA - Region: 1 #movable_nodes =      601 movable_node_area =      37.6, placeable_area =   50700.0, filler_node_area =   50662.4, #fillers =  405299, filler sizes =0.3536x0.353553

[INFO   ] DREAMPlaceFPGA - Region: 3 #movable_nodes =        2 movable_node_area =      10.0, placeable_area =    3600.0, filler_node_area =    3590.0, #fillers =     718, filler sizes = 1x5

[INFO   ] DREAMPlaceFPGA - reading benchmark takes 1.70551 seconds
[WARNING] DREAMPlaceFPGA - net weights are all the same, ignored
[INFO   ] DREAMPlaceFPGA - use nesterov optimizer
[INFO   ] DREAMPlaceFPGA - iter:    0, HPWL 1.499825E+03, Overflow [9.751E-01, 9.165E-01, 0.000E+00, 1.000E+00], time 29.711ms

<<SNIP>>

[INFO   ] DREAMPlaceFPGA - iter:  662, HPWL 4.606599E+03, Overflow [1.064E-01, 1.749E-02, 0.000E+00, 0.000E+00], time 24.936ms
[INFO   ] DREAMPlaceFPGA - iter:  663, HPWL 4.619926E+03, Overflow [9.856E-02, 2.062E-02, 0.000E+00, 0.000E+00], time 24.348ms
[INFO   ] DREAMPlaceFPGA - Lgamma stopping criteria: 663 > 100 and (( OVFL: 0.0985644 < 0.1; 0.0206154 < 0.1; 0 < 0.2; 0 < 0.2 and HPWL 4619.93 > 4606.6 ) or 1.66807 < 1.0) and DSP/RAM block legal iter 87 >= 5
Preclusters: 582 (582 + 0) Initialization completed in 0.002 seconds
RipUP & Greedy LG on 1352 insts (984 LUTs + 368 FFs) takes 0.558 seconds
[INFO   ] DREAMPlaceFPGA - legalization takes 2.009 seconds
[INFO   ] DREAMPlaceFPGA - iter:  664, HPWL 5.225543E+03, time 0.288ms
[INFO   ] DREAMPlaceFPGA - Placement completed in 61.65 seconds
[INFO   ] DREAMPlaceFPGA - writing to ./design/design.final.pl
[INFO   ] DREAMPlaceFPGA - write placement solution takes 0.008 seconds
[INFO   ] DREAMPlaceFPGA - Detailed Placement not run
[INFO   ] DREAMPlaceFPGA - Completed Placement in 61.848 seconds
[INFO   ] DREAMPlaceFPGA - Start writing solution to Interchange Format(IF)
Traceback (most recent call last):
  File "..../dreamplacefpga/Placer.py", line 130, in <module>
    placeFPGA(params)
  File "..../dreamplacefpga/Placer.py", line 93, in placeFPGA
    phys_netlist = db2phys.build_physicalnetlist(placedb, params)
  File "..../dreamplacefpga/IFWriter.py", line 2011, in build_physicalnetlist
    for key, value in pinmap[cell_type][site_type, bel_name].items():
KeyError: 'RAMB18E1'