@@ -1915,7 +1915,7 @@ INSN(fd_prefix) {XY_PREFIX(IY)}
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/*-----------------------------------------------------------------------.
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| Instructions with the two-byte prefix DDCBh or FDCBh increment R by 2, |
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| as only the prefix is fetched by opcode fetch operations (M1 cycles). |
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- | The remaining wto bytes are fetched by normal memory read operations. |
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+ | The remaining two bytes are fetched by normal memory read operations. |
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'=======================================================================*/
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INSN (xy_cb_prefix )
@@ -1928,8 +1928,8 @@ INSN(xy_cb_prefix)
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/*-----------------------------------------------------------------------------.
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| In a sequence of prefixes DDh and/or FDh, it is the last one that counts, as |
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| each prefix disables and replaces the previous one. No matter how long the |
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- | sequence is, interrupts can only be responded after all prefixes are fetched |
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- | and the final instruction is executed. Each prefix consumes 4 T-states. |
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+ | sequence is, interrupts can only be responded to after all prefixes are |
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+ | fetched and the final instruction is executed. Each prefix takes 4 T-states. |
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'=============================================================================*/
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INSN (xy_xy )
@@ -1975,7 +1975,7 @@ INSN(xy_xy)
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/* MARK: - Instructions: Illegal */
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/*----------------------------------------------------------------.
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- | The CPU ignores illegal opcodes prefixed with EDh; in practice, |
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+ | The CPU ignores illegal opcodes prefixed with EDh. In practice, |
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| they are all equivalent to two `nop` instructions (8 T-states). |
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'================================================================*/
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@@ -1988,11 +1988,11 @@ INSN(ed_illegal)
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}
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- /*------------------------------------------------------------------------ .
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- | Illegal opcodes with the prefix DDh or FDh cause the CPU to ignore the |
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- | prefix, i.e., the byte immediately following the prefix is interpreted |
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- | as the first byte of a new instruction. The prefix consumes 4 T-states. |
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- '======================================================================== */
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+ /*-----------------------------------------------------------------------.
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+ | Illegal opcodes with the prefix DDh or FDh cause the CPU to ignore the |
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+ | prefix, i.e., the byte immediately following the prefix is interpreted |
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+ | as the first byte of a new instruction. The prefix takes 4 T-states. |
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+ '=======================================================================*/
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INSN (xy_illegal )
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{
@@ -2191,8 +2191,8 @@ Z80_API void z80_nmi(Z80 *self)
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self -> cycles += insn_table [DATA [0 ] = FETCH_OPCODE (PC )](self );
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}
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- R = R_ALL ; /* restore R7 bit */
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- return self -> cycles ; /* return consumed cycles */
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+ R = R_ALL ; /* restore R7 bit */
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+ return self -> cycles ;
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}
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#endif
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@@ -2433,10 +2433,10 @@ Z80_API zusize z80_run(Z80 *self, zusize cycles)
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| An instruction supplied via the data bus is executed. Its first byte is |
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| read during the INT acknowledge cycle (INTA). If it is an opcode prefix, |
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| additional M-cycles of this kind are produced until the final opcode of |
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- | the instruction is fetched [1]. Each INT acknowledge cycle consumes as |
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- | many T-states as its normal M1 counterpart (the opcode fetch M-cycle) |
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- | plus the 2 wait T-states mentioned above [1]. Subsequent bytes of the |
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- | instruction are fetched by using normal memory read M-cycles [1,2], |
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+ | the instruction is fetched [1]. Each INT acknowledge cycle takes as many |
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+ | T-states as its normal M1 counterpart (the opcode fetch M-cycle) plus |
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+ | the 2 wait T-states mentioned above [1]. Subsequent bytes of the |
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+ | instruction are fetched by using normal memory read M-cycles [1,2], |
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| during which the interrupting I/O device must still supply the data [2]. |
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| The PC register, however, remains at its pre-interrupt state, not being |
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| incremented as a result of the instruction fetch [1,2]. |
@@ -2692,8 +2692,8 @@ Z80_API zusize z80_run(Z80 *self, zusize cycles)
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self -> cycles += insn_table [DATA [0 ] = FETCH_OPCODE (PC )](self );
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}
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- R = R_ALL ; /* restore R7 bit */
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- return self -> cycles ; /* return consumed cycles */
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+ R = R_ALL ; /* restore R7 bit */
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+ return self -> cycles ;
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}
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