Databus mapping in the weird z80 way (to reduce wires crossing)

Author: rejunity

src/ci2406_z80.v

@@ -76,6 +76,7 @@ module ci2406_z80(
     // 16 output address bus pins
     assign io_oeb[23:8]     = {16{1'b0}};       // 0 = Output
     // 8 bidirectional data bus pins
+
     assign io_oeb[31:24]    = {8{~data_oe}};    // 0 = Output | 1 = Input
     // 4 input control pins
     assign io_oeb[35:32]    = {4{1'b1}};        // 1 = Input
@@ -90,8 +91,18 @@ module ci2406_z80(
         .int_n   (io_in [32]),
         .nmi_n   (io_in [33]),
         .busrq_n (io_in [35]),
-        .di      (io_in [31:24]),
-        .dout    (io_out[31:24]),
+        // Z80 has peculiar data bus pin order, keep it to minimize wire crossing on the DIP40 PCB
+        // Also see: http://www.righto.com/2014/09/why-z-80s-data-pins-are-scrambled.html
+        //  D7 - io[29]
+        //  D6 - io[27]
+        //  D5 - io[26]
+        //  D4 - io[24]
+        //  D3 - io[25]
+        //  D2 - io[28]
+        //  D1 - io[31]
+        //  D0 - io[30]
+        .di      ({io_in [29], io_in [27], io_in [26], io_in [24], io_in [25], io_in [28], io_in [31], io_in [30]}),
+        .dout    ({io_out[29], io_out[27], io_out[26], io_out[24], io_out[25], io_out[28], io_out[31], io_out[30]}),
         .doe     (data_oe),
         .A       (io_out[23:8]),
         .halt_n  (io_out[0]),

test_chipignite/tb.v

@@ -22,12 +22,51 @@ module tb ();
   wire [3:0]  controls_in;
   wire [7:0]  controls_out  = io_out[7:0];
   wire [15:0] addr          = io_out[23:8];
-  wire [7:0]  data_in;
-  wire [7:0]  data_out      = io_out[31:24];
-  wire [7:0]  data_oe       =~io_oeb[31:24];
+
   assign io_in [35:32] = controls_in;
-  assign io_in [31:24] = data_in;
-  
+
+  // Z80 has a peculiar order of the pins for the data bus
+  //  <->     D4 | io[24]
+  //  <->     D3 | io[25]
+  //  <->     D5 | io[26]
+  //  <->     D6 | io[27]
+  //     VCC_5V0 |       
+  //  <->     D2 | io[28]
+  //  <->     D7 | io[29]
+  //  <->     D0 | io[30]
+  //  <->     D1 | io[31]
+
+  wire [7:0]  data_in;
+  wire [7:0]  data_out;
+  wire [7:0]  data_oe;
+
+  assign io_in [24] = data_in[4];
+  assign io_in [25] = data_in[3];
+  assign io_in [26] = data_in[5];
+  assign io_in [27] = data_in[6];
+  assign io_in [28] = data_in[2];
+  assign io_in [29] = data_in[7];
+  assign io_in [30] = data_in[0];
+  assign io_in [31] = data_in[1];
+
+  assign data_out[4] = io_out[24];
+  assign data_out[3] = io_out[25];
+  assign data_out[5] = io_out[26];
+  assign data_out[6] = io_out[27];
+  assign data_out[2] = io_out[28];
+  assign data_out[7] = io_out[29];
+  assign data_out[0] = io_out[30];
+  assign data_out[1] = io_out[31];
+
+  assign data_oe [4] = ~io_oeb[24];
+  assign data_oe [3] = ~io_oeb[25];
+  assign data_oe [5] = ~io_oeb[26];
+  assign data_oe [6] = ~io_oeb[27];
+  assign data_oe [2] = ~io_oeb[28];
+  assign data_oe [7] = ~io_oeb[29];
+  assign data_oe [0] = ~io_oeb[30];
+  assign data_oe [1] = ~io_oeb[31];
+
   // Replace tt_um_example with your module name:
   ci2406_z80 user_project (
       // Include power ports for the Gate Level test: