Optional half cycle earlier MREQ, IORQ, RD, WR signals

Author: rejunity

src/ci2406_z80.v

@@ -257,7 +257,9 @@ module ci2406_z80(
         .iorq_n  (io_out[34]),
         .rd_n    (io_out[ 2]),
         .wr_n    (io_out[ 3]),
-        .rfsh_n  (io_out[ 5])
+        .rfsh_n  (io_out[ 5]),
+        
+        .early_signals(custom_settings[0])
     );
 endmodule
 
@@ -282,9 +284,26 @@ module z80 (
     output wire         wr_n,
     output wire         rfsh_n,
     output wire         halt_n,
-    output wire         busak_n
+    output wire         busak_n,
+
+    input wire          early_signals
 );
 
+    wire         normal_mreq_n;
+    wire         normal_iorq_n;
+    wire         normal_rd_n;
+    wire         normal_wr_n;
+
+    wire         early_mreq_n;
+    wire         early_iorq_n;
+    wire         early_rd_n;
+    wire         early_wr_n;
+
+    assign mreq_n = early_signals ? early_mreq_n : normal_mreq_n;
+    assign iorq_n = early_signals ? early_iorq_n : normal_iorq_n;
+    assign rd_n   = early_signals ? early_rd_n   : normal_rd_n;
+    assign wr_n   = early_signals ? early_wr_n   : normal_wr_n;
+
     tv80s #(
         .Mode(0),   // Z80 mode
         .T2Write(1),// wr_n active in T2
@@ -298,10 +317,14 @@ module z80 (
         .nmi_n (nmi_n),
         .busrq_n (busrq_n),
         .m1_n (m1_n),
-        .mreq_n (mreq_n),
-        .iorq_n (iorq_n),
-        .rd_n (rd_n),
-        .wr_n (wr_n),
+        .mreq_n (normal_mreq_n),
+        .iorq_n (normal_iorq_n),
+        .rd_n (normal_rd_n),
+        .wr_n (normal_wr_n),
+        .early_mreq_n (early_mreq_n),
+        .early_iorq_n (early_iorq_n),
+        .early_rd_n (early_rd_n),
+        .early_wr_n (early_wr_n),
         .rfsh_n (rfsh_n),
         .halt_n (halt_n),
         .busak_n (busak_n),

src/tv80/tv80s.v

@@ -27,6 +27,7 @@
 module tv80s (/*AUTOARG*/
   // Outputs
   m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
+  early_mreq_n, early_iorq_n, early_rd_n, early_wr_n, 
   // Inputs
   reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di, cen,
   // Data bus state
@@ -50,6 +51,12 @@ module tv80s (/*AUTOARG*/
   output        iorq_n;
   output        rd_n;
   output        wr_n;
+
+  output        early_mreq_n;
+  output        early_iorq_n;
+  output        early_rd_n;
+  output        early_wr_n;
+
   output        rfsh_n;
   output        halt_n;
   output        busak_n;
@@ -62,6 +69,11 @@ module tv80s (/*AUTOARG*/
   reg           rd_n;
   reg           wr_n;
 
+  reg           early_mreq_n;
+  reg           early_iorq_n;
+  reg           early_rd_n;
+  reg           early_wr_n;
+
   wire          intcycle_n;
   wire          no_read;
   output        write;
@@ -161,5 +173,64 @@ module tv80s (/*AUTOARG*/
         end // else: !if(!reset_n)
     end // always @ (posedge clk or negedge reset_n)
 
+  always @(negedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        begin
+          early_rd_n   <= 1'b1;
+          early_wr_n   <= 1'b1;
+          early_iorq_n <= 1'b1;
+          early_mreq_n <= 1'b1;
+        end
+      else if(cen)
+        begin
+          early_rd_n <= 1'b1;
+          early_wr_n <= 1'b1;
+          early_iorq_n <= 1'b1;
+          early_mreq_n <= 1'b1;
+          if (mcycle[0])
+            begin
+              if (tstate[1] || (tstate[2] && wait_n == 1'b0))
+                begin
+                  early_rd_n <= ~ intcycle_n;
+                  early_mreq_n <= ~ intcycle_n;
+                  early_iorq_n <= intcycle_n;
+                end
+            `ifdef TV80_REFRESH
+              if (tstate[3])
+                early_mreq_n <= 1'b0;
+            `endif
+            end // if (mcycle[0])
+          else
+            begin
+              if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
+                begin
+                  early_rd_n <= 1'b0;
+                  early_iorq_n <= ~ iorq;
+                  early_mreq_n <= iorq;
+                end
+              if (T2Write == 0)
+                begin
+                  if (tstate[2] && write == 1'b1)
+                    begin
+                      early_wr_n <= 1'b0;
+                      early_iorq_n <= ~ iorq;
+                      early_mreq_n <= iorq;
+                    end
+                end
+              else
+                begin
+                  if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
+                    begin
+                      early_wr_n <= 1'b0;
+                      early_iorq_n <= ~ iorq;
+                      early_mreq_n <= iorq;
+                  end
+                end // else: !if(T2write == 0)
+
+            end // else: !if(mcycle[0])
+        end // else: !if(!reset_n)
+    end // always @ (posedge clk or negedge reset_n)
+
 endmodule // t80s
 

test_chipignite/tb.v

@@ -15,6 +15,7 @@ module tb ();
   // Wire up the inputs and outputs:
   reg clk;
   reg rst_n;
+  reg [31:0] custom_settings;
   wire [35:0] io_in;
   wire [35:0] io_out;
   wire [35:0] io_oeb;
@@ -78,7 +79,9 @@ module tb ();
       .rst_n  (rst_n),    // not reset
       .io_in  (io_in),
       .io_out (io_out),
-      .io_oeb (io_oeb)
+      .io_oeb (io_oeb),
+
+      .custom_settings(custom_settings)
   );
 
 endmodule