Add Support for Vector Permutation Instructions

[kathlenemagnus-mips]

Add vector sequencer and execution support for the vector permutation instructions. At least 1 test should be added with an instruction from each category to verify proper sequencing. Some of these instruction types require reading up to 8 source registers to write to a single destination, which is not reasonable for sequencing. Need to set a reasonable limit on the number of source registers allowed per uop and come up with a creative way to sequence these more complex instructions. The solution may require that the uops be executed in order, which is ok.

• Vector Permutation Instructions: Integer Scalar Move Instructions
• Vector Permutation Instructions: Floating-Point Scalar Move Instructions
• Vector Permutation Instructions: Vector Slide Instructions
• Vector Permutation Instructions: Vector Register Gather Instructions
• Vector Permutation Instructions: Vector Compress Instruction
• Vector Permutation Instructions: Whole Vector Register Move

[kathlenemagnus]

I've hooked up all of these instructions to the vector uop generator, but I have not implemented sequencing for the "complex" permute instructions. The uop generation for these types of permutes is very dependent on the design of the permute execution unit. It would make a good intern project!

[govardhnn]

Hi @kathlenemagnus, I would like to know if I can come up with a design proposal and a test plan for the remaining Vector permutation instructions.

[kathlenemagnus]

Hi @kathlenemagnus, I would like to know if I can come up with a design proposal and a test plan for the remaining Vector permutation instructions.

Yes, that would be ok with me. We can discuss your proposal in an upcoming SIG meeting.