Readability of spec

[ubc-guy]

This is new to me, so I find the spec unapproachable as a new reader.

1. the spec title says "load-acquire" and "store-release", but the spec itself calls them "load atomic ordered" and "store atomic ordered"

2. the Note for load atomic states: "Load-atomic is similarly not seen as useful enough. Instead, users should suitably align their pointers so that ordinary load instructions suffice." First, it says it's not useful, so why is spec being introduced at all? Second, the second sentence tells me to use aligned pointers to get rid of the load atomics. is this why it's not useful? this is all very confusing to a new reader.

3. the actual behaviour of the load-acquire is not given in plain language. I cannot read SAIL code, and I shouldn't have to load up a C++ reference or Java reference to learn about atomics. I want to know what these instructions are supposed to do, but I can't figure it out from this spec.

4. the simple description that opens the load atomics is not sufficient on its own. it states "This instruction loads size bytes of memory from rs1 atomically. " What exactly does "atomically" mean in this context? Is this only dealing with the memory-read portion when a memory address is misaligned? Or is this dealing with the register-commit portion, where only the entire register will be updated atomically at once and never partially as might be done by a misaligned load? or am I completely confused?

5. I don't know what the aquire or release are referring to.

6. how is this different from LR/SC ? or do they work together? I'm expecting they are entirely different beasts, but can't really tell from the Zalasr writeup. Yet, the similarity of their names goes unmentioned and much is left to the imagination.

7. the cited document [1] does a better job explaining things, but that's not its purpose. the explanation in this spec can be much simpler and precise. Here is the most relevant section from that document:

"Informally, L.aq ensures that later memory operations become visible after the load; S.rl ensures that earlier memory operations become visible before the store, and no pair of these instructions is ever visibly reordered. Other reordering with non-acquire-or-release instructions is allowed. These instructions are not useful as fences to order non-acquire-or-release instructions amongbthemselves."

Unfortunately, this still doesn't explain why they are called "load atomic ordered" and "store atomic ordered" in this spec.

A spec should be self-contained -- one shouldn't have to go outside of the spec to figure things out -- especially if those references disappear or are not highly available works that are largely immutable (eg, another standard).

[mehnadnerd]

I've updated the spec to hopefully be clearer.
For more detail on load-acquire, store-release, and RVWMO in general, please refer to Chapter 17 (RVWMO), Appendices A (RVWMO Explanatory) and B (Formal Specification).