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TimmmmTimmmm
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Move extension scattered enum to single file
Having this distributed through the code can lead to slightly awkward dependency order issues. We need to keep it scattered though so e.g. CHERI can add its extensions.
1 parent e8a4c38 commit c855281

30 files changed

+112
-53
lines changed

Diff for: ‎Makefile

+2-2
Original file line numberDiff line numberDiff line change
@@ -106,11 +106,11 @@ SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
106106
SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail
107107

108108
SAIL_ARCH_SRCS = $(PRELUDE)
109-
SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail
109+
SAIL_ARCH_SRCS += riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail
110110
SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
111111
SAIL_ARCH_SRCS += riscv_sstc.sail
112112
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
113-
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
113+
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
114114
SAIL_ARCH_SRCS += riscv_types_kext.sail # Shared/common code for the cryptography extension.
115115

116116
SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail

Diff for: ‎model/riscv_extensions.sail

+107
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,107 @@
1+
/*=======================================================================================*/
2+
/* This Sail RISC-V architecture model, comprising all files and */
3+
/* directories except where otherwise noted is subject the BSD */
4+
/* two-clause license in the LICENSE file. */
5+
/* */
6+
/* SPDX-License-Identifier: BSD-2-Clause */
7+
/*=======================================================================================*/
8+
9+
scattered enum extension
10+
11+
// Note, these are sorted according to the canonical ordering vaguely described
12+
// in the `Subset Naming Convention` section of the unprivileged spec.
13+
14+
// Integer Multiplication and Division; not Machine!
15+
enum clause extension = Ext_M
16+
// Single-Precision Floating-Point
17+
enum clause extension = Ext_F
18+
// Double-Precision Floating-Point
19+
enum clause extension = Ext_D
20+
// Compressed Instructions
21+
enum clause extension = Ext_C
22+
// Bit Manipulation
23+
enum clause extension = Ext_B
24+
// Vector Operations
25+
enum clause extension = Ext_V
26+
// Supervisor
27+
enum clause extension = Ext_S
28+
// User
29+
enum clause extension = Ext_U
30+
31+
// Cache-Block Management Instructions
32+
enum clause extension = Ext_Zicbom
33+
// Cache-Block Zero Instructions
34+
enum clause extension = Ext_Zicboz
35+
// Integer Conditional Operations
36+
enum clause extension = Ext_Zicond
37+
// Instruction-Fetch Fence
38+
enum clause extension = Ext_Zifencei
39+
// Hardware Performance Counters
40+
enum clause extension = Ext_Zihpm
41+
42+
// Multiplication and Division: Multiplication only
43+
enum clause extension = Ext_Zmmul
44+
// Atomic Memory Operations
45+
46+
enum clause extension = Ext_Zaamo
47+
// Byte and Halfword Atomic Memory Operations
48+
enum clause extension = Ext_Zabha
49+
// Load-Reserved/Store-Conditional Instructions
50+
enum clause extension = Ext_Zalrsc
51+
52+
// Additional Floating-Point Instructions
53+
enum clause extension = Ext_Zfa
54+
// Half-Precision Floating-Point
55+
enum clause extension = Ext_Zfh
56+
// Minimal Half-Precision Floating-Point
57+
enum clause extension = Ext_Zfhmin
58+
// Floating-Point in Integer Registers (single precision)
59+
enum clause extension = Ext_Zfinx
60+
61+
// Floating-Point in Integer Registers (double precision)
62+
enum clause extension = Ext_Zdinx
63+
64+
// Code Size Reduction: compressed instructions excluding floating point loads and stores
65+
enum clause extension = Ext_Zca
66+
// Code Size Reduction: additional 16-bit aliases
67+
enum clause extension = Ext_Zcb
68+
// Code Size Reduction: compressed double precision floating point loads and stores
69+
enum clause extension = Ext_Zcd
70+
// Code Size Reduction: compressed single precision floating point loads and stores
71+
enum clause extension = Ext_Zcf
72+
73+
// Bit Manipulation: Address generation
74+
enum clause extension = Ext_Zba
75+
// Bit Manipulation: Basic bit-manipulation
76+
enum clause extension = Ext_Zbb
77+
// Bit Manipulation: Carry-less multiplication
78+
enum clause extension = Ext_Zbc
79+
// Bit Manipulation: Bit-manipulation for Cryptography
80+
enum clause extension = Ext_Zbkb
81+
// Bit Manipulation: Carry-less multiplication for Cryptography
82+
enum clause extension = Ext_Zbkc
83+
// Bit Manipulation: Crossbar permutations
84+
enum clause extension = Ext_Zbkx
85+
// Bit Manipulation: Single-bit instructions
86+
enum clause extension = Ext_Zbs
87+
88+
// Scalar & Entropy Source Instructions: NIST Suite: AES Decryption
89+
enum clause extension = Ext_Zknd
90+
// Scalar & Entropy Source Instructions: NIST Suite: AES Encryption
91+
enum clause extension = Ext_Zkne
92+
// Scalar & Entropy Source Instructions: NIST Suite: Hash Function Instructions
93+
enum clause extension = Ext_Zknh
94+
// Scalar & Entropy Source Instructions: Entropy Source Extension
95+
enum clause extension = Ext_Zkr
96+
// Scalar & Entropy Source Instructions: ShangMi Suite: SM4 Block Cipher Instructions
97+
enum clause extension = Ext_Zksed
98+
// Scalar & Entropy Source Instructions: ShangMi Suite: SM3 Hash Cipher Instructions
99+
enum clause extension = Ext_Zksh
100+
101+
// Floating-Point in Integer Registers (half precision)
102+
enum clause extension = Ext_Zhinx
103+
104+
// Supervisor-mode Timer Interrupts
105+
enum clause extension = Ext_Sstc
106+
// Fine-Grained Address-Translation Cache Invalidation
107+
enum clause extension = Ext_Svinval

Diff for: ‎model/riscv_fdext_control.sail

-5
Original file line numberDiff line numberDiff line change
@@ -15,13 +15,8 @@
1515

1616
/* **************************************************************** */
1717

18-
enum clause extension = Ext_F
1918
function clause extensionEnabled(Ext_F) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)
20-
21-
enum clause extension = Ext_D
2219
function clause extensionEnabled(Ext_D) = (misa[D] == 0b1) & (mstatus[FS] != 0b00) & flen >= 64
23-
24-
enum clause extension = Ext_Zfinx
2520
function clause extensionEnabled(Ext_Zfinx) = sys_enable_zfinx()
2621

2722
/* Floating Point CSRs */

Diff for: ‎model/riscv_insts_aext.sail

+1-3
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
/* This file specifies the atomic instructions in the 'A' extension. */
1111

1212
/* ****************************************************************** */
13-
enum clause extension = Ext_Zabha
13+
1414
function clause extensionEnabled(Ext_Zabha) = true
1515

1616
// Some print utils for lr/sc.
@@ -53,7 +53,6 @@ function amo_width_valid(size : word_width) -> bool = {
5353
}
5454

5555
/* ****************************************************************** */
56-
enum clause extension = Ext_Zalrsc
5756
function clause extensionEnabled(Ext_Zalrsc) = misa[A] == 0b1
5857

5958
union clause ast = LOADRES : (bool, bool, regidx, word_width, regidx)
@@ -168,7 +167,6 @@ mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd)
168167
<-> "sc." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")"
169168

170169
/* ****************************************************************** */
171-
enum clause extension = Ext_Zaamo
172170
function clause extensionEnabled(Ext_Zaamo) = misa[A] == 0b1
173171

174172
union clause ast = AMO : (amoop, bool, bool, regidx, regidx, word_width, regidx)

Diff for: ‎model/riscv_insts_base.sail

-3
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,7 @@
99
/* ****************************************************************** */
1010
/* This file specifies the instructions in the base integer set. */
1111

12-
enum clause extension = Ext_C
1312
function clause extensionEnabled(Ext_C) = misa[C] == 0b1
14-
15-
enum clause extension = Ext_Zca
1613
function clause extensionEnabled(Ext_Zca) = extensionEnabled(Ext_C)
1714

1815
/* ****************************************************************** */

Diff for: ‎model/riscv_insts_dext.sail

-1
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,6 @@ function fle_D (v1, v2, is_quiet) = {
224224
/* **************************************************************** */
225225
/* Helper functions for 'encdec()' */
226226

227-
enum clause extension = Ext_Zdinx
228227
function clause extensionEnabled(Ext_Zdinx) = sys_enable_zfinx() & flen >= 64
229228

230229
function haveDoubleFPU() -> bool = extensionEnabled(Ext_D) | extensionEnabled(Ext_Zdinx)

Diff for: ‎model/riscv_insts_fext.sail

-2
Original file line numberDiff line numberDiff line change
@@ -26,10 +26,8 @@
2626
/* **************************************************************** */
2727

2828
// TODO: Add config flags to control Zfh and Zfhmin
29-
enum clause extension = Ext_Zfh
3029
function clause extensionEnabled(Ext_Zfh) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)
3130

32-
enum clause extension = Ext_Zfhmin
3331
// Zfhmin is a subset of Zfh. This can be changed to extensionEnabled(Ext_Zfh) | sys_enable_zfhmin() when more configuration is implemented.
3432
function clause extensionEnabled(Ext_Zfhmin) = extensionEnabled(Ext_Zfh)
3533

Diff for: ‎model/riscv_insts_mext.sail

-2
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,7 @@
1111

1212
/* ****************************************************************** */
1313

14-
enum clause extension = Ext_M
1514
function clause extensionEnabled(Ext_M) = misa[M] == 0b1
16-
enum clause extension = Ext_Zmmul
1715
function clause extensionEnabled(Ext_Zmmul) = true
1816

1917

Diff for: ‎model/riscv_insts_svinval.sail

-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Svinval
109
function clause extensionEnabled(Ext_Svinval) = sys_enable_svinval()
1110

1211
union clause ast = SINVAL_VMA : (regidx, regidx)

Diff for: ‎model/riscv_insts_zba.sail

-3
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,7 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_B
109
function clause extensionEnabled(Ext_B) = misa[B] == 0b1
11-
12-
enum clause extension = Ext_Zba
1310
function clause extensionEnabled(Ext_Zba) = true | extensionEnabled(Ext_B)
1411

1512
/* ****************************************************************** */

Diff for: ‎model/riscv_insts_zbb.sail

-3
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,7 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zbb
109
function clause extensionEnabled(Ext_Zbb) = true | extensionEnabled(Ext_B)
11-
12-
enum clause extension = Ext_Zbkb
1310
function clause extensionEnabled(Ext_Zbkb) = true
1411

1512
/* ****************************************************************** */

Diff for: ‎model/riscv_insts_zbc.sail

-3
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,7 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zbc
109
function clause extensionEnabled(Ext_Zbc) = true
11-
12-
enum clause extension = Ext_Zbkc
1310
function clause extensionEnabled(Ext_Zbkc) = true
1411

1512
/* ****************************************************************** */

Diff for: ‎model/riscv_insts_zbkx.sail

-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zbkx
109
function clause extensionEnabled(Ext_Zbkx) = true
1110

1211
/* ****************************************************************** */

Diff for: ‎model/riscv_insts_zbs.sail

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Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zbs
109
function clause extensionEnabled(Ext_Zbs) = true | extensionEnabled(Ext_B)
1110

1211
/* ****************************************************************** */

Diff for: ‎model/riscv_insts_zcb.sail

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@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zcb
109
function clause extensionEnabled(Ext_Zcb) = sys_enable_zcb() & extensionEnabled(Ext_Zca)
1110

1211
union clause ast = C_LBU : (bits(2), cregidx, cregidx)

Diff for: ‎model/riscv_insts_zcd.sail

-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zcd
109
function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (xlen == 32 | xlen == 64)
1110

1211
union clause ast = C_FLDSP : (bits(6), regidx)

Diff for: ‎model/riscv_insts_zcf.sail

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Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@
1515

1616
/* ****************************************************************** */
1717

18-
enum clause extension = Ext_Zcf
1918
function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & xlen == 32
2019

2120
union clause ast = C_FLWSP : (bits(6), regidx)

Diff for: ‎model/riscv_insts_zfa.sail

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Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zfa
109
function clause extensionEnabled(Ext_Zfa) = true
1110

1211
/* FLI.H */

Diff for: ‎model/riscv_insts_zfh.sail

-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zhinx
109
function clause extensionEnabled(Ext_Zhinx) = sys_enable_zfinx()
1110

1211
/* **************************************************************** */

Diff for: ‎model/riscv_insts_zicbom.sail

-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@
88

99
// Cache Block Operations - Management
1010

11-
enum clause extension = Ext_Zicbom
1211
function clause extensionEnabled(Ext_Zicbom) = sys_enable_zicbom()
1312

1413
function cbo_clean_flush_enabled(p : Privilege) -> bool = feature_enabled_for_priv(p, menvcfg[CBCFE][0], senvcfg[CBCFE][0])

Diff for: ‎model/riscv_insts_zicboz.sail

-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@
88

99
// Cache Block Operations - Zero
1010

11-
enum clause extension = Ext_Zicboz
1211
function clause extensionEnabled(Ext_Zicboz) = sys_enable_zicboz()
1312

1413
function cbo_zero_enabled(p : Privilege) -> bool = feature_enabled_for_priv(p, menvcfg[CBZE][0], senvcfg[CBZE][0])

Diff for: ‎model/riscv_insts_zicond.sail

-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
/* SPDX-License-Identifier: BSD-2-Clause */
77
/*=======================================================================================*/
88

9-
enum clause extension = Ext_Zicond
109
function clause extensionEnabled(Ext_Zicond) = true
1110

1211
union clause ast = ZICOND_RTYPE : (regidx, regidx, regidx, zicondop)

Diff for: ‎model/riscv_insts_zifencei.sail

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
/* This file specifies the instructions in the 'Zifencei' extension. */
1111

1212
/* ****************************************************************** */
13-
enum clause extension = Ext_Zifencei
13+
1414
function clause extensionEnabled(Ext_Zifencei) = true
1515

1616
union clause ast = FENCEI : unit

Diff for: ‎model/riscv_insts_zkn.sail

+1-3
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
* Scalar Cryptography Extension - Scalar SHA256 instructions (RV32/RV64)
1111
* ----------------------------------------------------------------------
1212
*/
13-
enum clause extension = Ext_Zknh
13+
1414
function clause extensionEnabled(Ext_Zknh) = true
1515

1616
union clause ast = SHA256SIG0 : (regidx, regidx)
@@ -75,7 +75,6 @@ function clause execute (SHA256SUM1(rs1, rd)) = {
7575
* ----------------------------------------------------------------------
7676
*/
7777

78-
enum clause extension = Ext_Zkne
7978
function clause extensionEnabled(Ext_Zkne) = true
8079

8180
union clause ast = AES32ESMI : (bits(2), regidx, regidx, regidx)
@@ -118,7 +117,6 @@ function clause execute (AES32ESI (bs, rs2, rs1, rd)) = {
118117
* ----------------------------------------------------------------------
119118
*/
120119

121-
enum clause extension = Ext_Zknd
122120
function clause extensionEnabled(Ext_Zknd) = true
123121

124122
union clause ast = AES32DSMI : (bits(2), regidx, regidx, regidx)

Diff for: ‎model/riscv_insts_zks.sail

-2
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@
1111
* ----------------------------------------------------------------------
1212
*/
1313

14-
enum clause extension = Ext_Zksh
1514
function clause extensionEnabled(Ext_Zksh) = true
1615

1716
union clause ast = SM3P0 : (regidx, regidx)
@@ -48,7 +47,6 @@ function clause execute (SM3P1(rs1, rd)) = {
4847
* ----------------------------------------------------------------------
4948
*/
5049

51-
enum clause extension = Ext_Zksed
5250
function clause extensionEnabled(Ext_Zksed) = true
5351

5452
union clause ast = SM4ED : (bits(2), regidx, regidx, regidx)

Diff for: ‎model/riscv_sys_regs.sail

-3
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,6 @@ val sys_enable_zicboz = pure "sys_enable_zicboz" : unit -> bool
118118
val sys_enable_sstc = pure "sys_enable_sstc" : unit -> bool
119119

120120
// Supervisor timecmp
121-
enum clause extension = Ext_Sstc
122121
function clause extensionEnabled(Ext_Sstc) = sys_enable_sstc()
123122

124123
/* This function allows an extension to veto a write to Misa
@@ -146,10 +145,8 @@ function clause is_CSR_defined(0x301) = true // misa
146145
function clause read_CSR(0x301) = misa.bits
147146
function clause write_CSR(0x301, value) = { misa = legalize_misa(misa, value); misa.bits }
148147

149-
enum clause extension = Ext_U
150148
function clause extensionEnabled(Ext_U) = misa[U] == 0b1
151149

152-
enum clause extension = Ext_S
153150
function clause extensionEnabled(Ext_S) = misa[S] == 0b1
154151

155152
/*

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