Add support for the Zvkg extension #241
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…iscv#191) * V extension general framework and configuration setting instructions * Update model/riscv_insts_vext_utils.sail fix a typo Co-authored-by: Nicolas Brunie <[email protected]> Signed-off-by: BrighterW <[email protected]> * Update model/riscv_insts_vext_vset.sail * Revisions after Nov 22 meeting * Update effect matching for functions in riscv_vlen.sail * Fix code formatting issues * Update model/riscv_insts_vext_utils.sail Co-authored-by: Jessica Clarke <[email protected]> Signed-off-by: Xinlai Wan <[email protected]> * Fix coding style issues * Update vset instructions Signed-off-by: BrighterW <[email protected]> Signed-off-by: Xinlai Wan <[email protected]> Co-authored-by: Nicolas Brunie <[email protected]> Co-authored-by: Jessica Clarke <[email protected]>
* Add vector load / store instructions * Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code * Update vstart setting in vector load / store instructions * Remove unnecessary assert statements in vector instructions * Fix bugs in vleff instructions and revise coding styles * Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure
* Add vector arithmetic & mask instructions * Update vector EEW and EMUL checking function * Add vector instruction illegal check functions * Adjust code formatting for vector instruction illegal check functions Merge approved by team at tech-golden-model meeting on 2023-03-14.
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Updated the PR:
This update is adjusting the implementation to match the Spike implenentation and as a follow-up, ACT Signatures matching. |
* Add vector floating-point instructions * Update vector floating-point conversion instructions * Update copyright headers for vector extension code --------- Co-authored-by: xwan <[email protected]>
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Rebased from |
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* Add vector mask and reduction instructions * Fix register overlap check in vector mask instructions --------- Co-authored-by: xwan <[email protected]>
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July 11, 2023 09:30
VGHSH.VV: Add-Multiply over GHASH Galois-Field This instruction treats all inputs and outputs as 128-bit polynomials and performs operations over GF[2]. The next partial hash(Y[i+1]) is produced by adding the current partial hash(Y[i]) to the cipher text block and then multiplying this sum by the Hash Subkey(H). Since the bits in the bytes are reversed, this instruction internally performs a bit swap within bytes to put the bits in the standard ordering. VGMUL.VV: Vector Multiply over GHASH Galois-Field Same as vghsh.vv, this instruction treats all inputs and outputs as 128-bit polynomials and performs operations over GF[2]. The multiplication is a caryless multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial. Since the bits in the bytes are reversed, this instruction internally performs a bit swap within bytes to put the bits in the standard ordering. Signed-off-by: Charalampos Mitrodimas <[email protected]>
Signed-off-by: Charalampos Mitrodimas <[email protected]>
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Implements the Zvkg (Vector GCM/GMAC) extension, as of version Draft: 20230303
The following instructions are included:
All instructions were tested with VLEN & ELEN being manually adjusted; results were compared with QEMU results of each instruction.
Current revision is rebased with the latest changes of
vector-devbranch.