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VM code doesn't check reserved bits of PTEs are zero #457
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That requirement doesn’t exist in older versions of the spec IIRC |
Ah maybe. It's in the 20211203 version (current ratified one linked from the risc-v website). |
20190608 (ratified v1.11) says just:
|
Welcome to extension versioning. The earlier spec is probably priv1.10, as
opposed to priv1.11 or priv1.12 or priv1.13
(which was just described in the Committee Chairs meeting- most of the
changes are really clarifications of behaviors,
or giving names to optional behaviors that previously had no name)
The imperas simulator has command line switches to handle each behaviors
(and more, for cases where someone implemented an unratified spec, and then
it got changed)
This will need a CLI (and eventually YAML) that describes which version of
the priv spec .
…On Wed, Apr 24, 2024 at 8:46 AM Jessica Clarke ***@***.***> wrote:
20190608 says just:
The PTE format for Sv39 is shown in Figure 4.18. Bits 9–0 have the same
meaning as for Sv32. Bits 63–54 are reserved for future use and must be
zeroed by software for forward compatibility.
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Yeah see #319. I would suggest that until we have flags for this it probably makes sense to implement the latest ratified version and add comments where there are differences between versions like here. I may have a go at implementing #319 at least for the privileged/unprivileged specs. Shouldn't be too hard. |
From the Sv39 spec:
The current code doesn't check these reserved bits at all.
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