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Remove vector of bools in vext #622

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@rez5427 rez5427 commented Nov 24, 2024

fix #554
emmm...
I will test the code with riscv-vector-tests later...
And to make sure assert('n > 0); is right

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github-actions bot commented Nov 24, 2024

Test Results

396 tests  ±0   396 ✅ ±0   0s ⏱️ ±0s
  4 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit 7eea7ac. ± Comparison against base commit 07fa23e.

♻️ This comment has been updated with latest results.

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rez5427 commented Nov 27, 2024

The 'n produced in here, and I believe it can't be 0.

/* num_elem means max(VLMAX,VLEN/SEW)) according to Section 5.4 of RVV spec */
val get_num_elem : (int, int) -> nat
function get_num_elem(LMUL_pow, SEW) = {
  let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;
  /* Ignore lmul < 1 so that the entire vreg is read, allowing all masking to
   * be handled in init_masked_result */
  let num_elem = 2 ^ (LMUL_pow_reg) * VLEN / SEW;
  assert(num_elem > 0);
  num_elem
}

And the result of this commit run with riscv-vector-tests is in here

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rez5427 commented Dec 3, 2024

I'm really curious about the code below...
The function get_num_elem has a assert inside that it returns a number bigger than 0. See get_num_elem function.
But in the code below, If it doesn't have a assert('n > 0);, It won't compile and shows a type error.
And I think is really silly for write assert('n > 0); like hundres of times.

Maybe this should be supported by sail to remember the range of a funtion return value? idk...

let num_elem = get_num_elem(LMUL_pow, SEW);

if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;
Type error:
model/riscv_insts_vext_arith.sail:58.31-64:
58 |  let vm_val  : bits('n)     = read_vmask(num_elem, vm, 0b00000);
   |                               ^-------------------------------^
   | Could not resolve quantifiers for read_vmask
   | * 'n > 0

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rez5427 and others added 6 commits December 4, 2024 15:07
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bacam commented Dec 4, 2024

I'm really curious about the code below... The function get_num_elem has a assert inside that it returns a number bigger than 0. See get_num_elem function. But in the code below, If it doesn't have a assert('n > 0);, It won't compile and shows a type error. And I think is really silly for write assert('n > 0); like hundres of times.

Maybe this should be supported by sail to remember the range of a funtion return value? idk...

It should work if you make get_num_elem's return type { 'n, 'n > 0. int('n)}. At the moment it's just nat, which allows zero.

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Timmmm commented Dec 4, 2024

But I would recommend not trying to fix the types in this PR! I started going down that route and you end up rewriting half the vector code and never finishing (I have also done the same for the virtual memory code, though that is a less code so I've almost finished). Let's use asserts temporarily and then we can gradually fix the types and remove the asserts.

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rez5427 commented Dec 14, 2024

I change the def below, change 'n >= 0 to 'n > 0. Because it all use get_num_elem to produce it.

val process_rfvv_widen: forall 'n 'm 'p, 'n > 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired
function process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) = {
function clause execute(RFVVTYPE(funct6, vm, vs2, vs1, vd)) = {
  let SEW      = get_sew();
  let LMUL_pow = get_lmul_pow();
  let num_elem_vs = get_num_elem(LMUL_pow, SEW);

  if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then
    process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow)
  else
    process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow)
}

let res : bool = match funct6 {
VVM_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1,
VVM_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])) < 0
VVM_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + (if vm_val[i] == bitone then 1 else 0) > 2 ^ SEW - 1,
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Can't this just be unsigned(vm_val[I])?

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I remember the last time I tried with unsigned(vm_val[I]), and unsigned take bits not bit, also tried with to_bits,but it also not take type bit. sorry for not mention that...

val unsigned = pure {
  ocaml: "uint",
  lem: "uint",
  interpreter: "uint",
  coq: "uint",
  lean: "BitVec.toNat",
  _: "sail_unsigned"
} : forall 'n. bits('n) -> range(0, 2 ^ 'n - 1)

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This generally looks good to me. There are a few more simplifications that I've pointed out (commented on the first instance only but there are often multiple).

Further cleanup can be done in a follow up

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Use bit vectors for read_vmask and read_vmask_carry
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