WAITCNT bitfield defintions (#209)

Co-authored-by: lifning <>

Author: lifning

Diff for: src/interrupts.rs

@@ -1,4 +1,4 @@
-use crate::macros::{pub_const_fn_new_zeroed, u16_bool_field};
+use crate::macros::{pub_const_fn_new_zeroed, u16_bool_field, u16_enum_field};
 
 /// A function you want called during an interrupt.
 pub type IrqFn = unsafe extern "C" fn(IrqBits);
@@ -45,5 +45,86 @@ impl IrqBits {
   }
 }
 
+#[derive(Debug, Clone, Copy, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
+#[repr(transparent)]
+pub struct WaitstateControl(pub u16);
+impl WaitstateControl {
+  pub_const_fn_new_zeroed!();
+  u16_enum_field!(0 - 1: SramFirstAccess, sram, with_sram);
+  u16_enum_field!(
+    2 - 3:
+    Waitstate0FirstAccess,
+    ws0_first_access,
+    with_ws0_first_access
+  );
+  // true = 2, false = 1
+  u16_bool_field!(4, ws0_second_access, with_ws0_second_access);
+  u16_enum_field!(
+    5 - 6:
+    Waitstate1FirstAccess,
+    ws1_first_access,
+    with_ws1_first_access
+  );
+  // true = 4, false = 1
+  u16_bool_field!(7, ws1_second_access, with_ws1_second_access);
+  u16_enum_field!(
+    8 - 9:
+    Waitstate2FirstAccess,
+    ws2_first_access,
+    with_ws2_first_access
+  );
+  // true = 8, false = 1
+  u16_bool_field!(10, ws2_second_access, with_ws2_second_access);
+  u16_enum_field!(
+    11 - 12:
+    PhiTerminalOutput,
+    phi_terminal_output,
+    with_phi_terminal_output
+  );
+  u16_bool_field!(14, game_pak_prefetch_buffer, with_game_pak_prefetch_buffer);
+  u16_bool_field!(15, game_pak_is_cgb, with_game_pak_is_cgb);
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u16)]
+pub enum SramFirstAccess {
+  Cycles4 = 0,
+  Cycles3 = 1,
+  Cycles2 = 2,
+  Cycles8 = 3,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u16)]
+pub enum Waitstate0FirstAccess {
+  Cycles4 = 0 << 2,
+  Cycles3 = 1 << 2,
+  Cycles2 = 2 << 2,
+  Cycles8 = 3 << 2,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u16)]
+pub enum Waitstate1FirstAccess {
+  Cycles4 = 0 << 5,
+  Cycles3 = 1 << 5,
+  Cycles2 = 2 << 5,
+  Cycles8 = 3 << 5,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u16)]
+pub enum Waitstate2FirstAccess {
+  Cycles4 = 0 << 8,
+  Cycles3 = 1 << 8,
+  Cycles2 = 2 << 8,
+  Cycles8 = 3 << 8,
+}
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u16)]
+pub enum PhiTerminalOutput {
+  Disabled = 0 << 11,
+  Freq4MHz = 1 << 11,
+  Freq8MHz = 2 << 11,
+  Freq16MHz = 3 << 11,
+}
+
 // TODO: might want to support bit ops. But it's not super important right now
 // since they can't be implented as const traits yet anyway.

Diff for: src/mmio.rs

@@ -186,7 +186,7 @@ def_mmio!(0x0400_0158 = JOYSTAT: VolAddress<u8, Safe, Safe>);
 
 def_mmio!(0x0400_0200 = IE: VolAddress<IrqBits, Safe, Safe>; "Interrupts Enabled: sets which interrupts will be accepted when a subsystem fires an interrupt");
 def_mmio!(0x0400_0202 = IF: VolAddress<IrqBits, Safe, Safe>; "Interrupts Flagged: reads which interrupts are pending, writing bit(s) will clear a pending interrupt.");
-def_mmio!(0x0400_0204 = WAITCNT: VolAddress<u16, Safe, Unsafe>; "Wait state control for interfacing with the ROM.\n\nThis can make reading the ROM give garbage when it's mis-configured!");
+def_mmio!(0x0400_0204 = WAITCNT: VolAddress<WaitstateControl, Safe, Unsafe>; "Wait state control for interfacing with the ROM.\n\nThis can make reading the ROM give garbage when it's mis-configured!");
 def_mmio!(0x0400_0208 = IME: VolAddress<bool, Safe, Safe>; "Interrupt Master Enable: Allows turning on/off all interrupts with a single access.");
 
 // mGBA Logging