refactor(rt): split bootloading assemble code into arch modules

Add `riscv_fpu` module.

Signed-off-by: Zhouqi Jiang <[email protected]>

Author: luojia65

.github/workflows/Cargo.yml

@@ -25,7 +25,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        TARGET: [riscv64imac-unknown-none-elf]
+        TARGET: [riscv64imac-unknown-none-elf, riscv64gc-unknown-none-elf]
         TOOLCHAIN: [nightly]
     steps:
       - uses: actions/checkout@v4

allwinner-rt/.cargo/config.toml

@@ -23,6 +23,10 @@ embedded-hal = "1.0.0"
 embedded-time = "0.12.1"
 nb = "1.1.0"
 plic = "0.0.2"
+cfg-if = "1.0.4"
+
+[build-dependencies]
+riscv-target-parser = "0.1.3"
 
 [features]
 default = ["nezha"]

allwinner-rt/Cargo.toml

@@ -1,6 +1,33 @@
+use riscv_target_parser::RiscvTarget;
 use std::{env, path::PathBuf};
 
 fn main() {
+    load_linker_script();
+    load_fpu_features();
+}
+
+fn load_fpu_features() {
+    // Adapted from `riscv-rt` crate.
+    // List of all possible RISC-V configurations to check for in allwinner-rt
+    const RISCV_CFG: [&str; 3] = ["riscvf", "riscvd", "riscvq"];
+    // Required until target_feature risc-v is stable and in-use (rust 1.75)
+    for ext in RISCV_CFG.iter() {
+        println!("cargo:rustc-check-cfg=cfg({ext})");
+    }
+    let target = env::var("TARGET").unwrap();
+    let cargo_flags = env::var("CARGO_ENCODED_RUSTFLAGS").unwrap();
+
+    if let Ok(target) = RiscvTarget::build(&target, &cargo_flags) {
+        for flag in target.rustc_flags() {
+            // Required until target_feature risc-v is stable and in-use
+            if RISCV_CFG.contains(&flag.as_str()) {
+                println!("cargo:rustc-cfg={}", flag.as_str());
+            }
+        }
+    }
+}
+
+fn load_linker_script() {
     let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
     let ld = &out.join("allwinner-rt.ld");
 
@@ -23,7 +50,7 @@ SECTIONS {
         KEEP(*(.head.meta))
     } > SRAM
     .text : ALIGN(4) {
-        KEEP(*(.text.entry))
+        *(.text.entry)
         *(.text .text.*)
     } > SRAM
     .rodata : ALIGN(8) {

allwinner-rt/build.rs

@@ -0,0 +1,36 @@
+/// Jump over head data to executable code.
+///
+/// TODO Andes start code.
+#[cfg(feature = "v821")]
+#[unsafe(naked)]
+#[unsafe(link_section = ".text.entry")]
+pub unsafe extern "C" fn start() -> ! {
+    const STACK_SIZE: usize = 8 * 1024;
+    #[unsafe(link_section = ".bss.uninit")]
+    static mut STACK: [u8; STACK_SIZE] = [0; STACK_SIZE];
+    core::arch::naked_asm!(
+        // Disable interrupt
+        "csrw   mie, zero",
+        // Prepare programming language stack
+        "la     sp, {stack}
+        li      t0, {stack_size}
+        add     sp, sp, t0",
+        // Clear `.bss` section
+        "la     t1, sbss
+        la      t2, ebss
+    3:  bgeu    t1, t2, 3f
+        sd      zero, 0(t1)
+        addi    t1, t1, 8
+        j       3b
+    3:  ",
+        // TODO Enable floating point unit
+        // Start Rust main function
+        "call   {main}",
+        // Platform halt if main function returns
+    "3: wfi
+        j       3b",
+        stack      =   sym STACK,
+        stack_size = const STACK_SIZE,
+        main       =   sym crate::main,
+    )
+}

allwinner-rt/examples/fn-main.rs

@@ -0,0 +1,15 @@
+#[cfg(riscvf)]
+pub unsafe extern "C" fn init_floating_point() {
+    unsafe {
+        core::arch::asm! {
+            "li     t0, 0x4000
+            li     t1, 0x2000
+            csrrc  x0, mstatus, t0
+            csrrs  x0, mstatus, t1
+            fscsr  x0",
+        }
+    }
+}
+
+#[cfg(not(riscvf))]
+pub unsafe extern "C" fn init_floating_point() {}

allwinner-rt/src/arch/andes_a27l2.rs

@@ -0,0 +1,61 @@
+/// Jump over head data to executable code.
+///
+/// # Safety
+///
+/// Naked function.
+///
+/// NOTE: `mxstatus` is a custom T-Head register. Do not confuse with `mstatus`.
+/// It allows for configuring special eXtensions. See further below for details.
+#[cfg(any(all(feature = "d1", target_arch = "riscv64"), doc))]
+#[unsafe(naked)]
+#[unsafe(link_section = ".text.entry")]
+pub unsafe extern "C" fn start() -> ! {
+    use super::riscv_fpu::init_floating_point;
+    use crate::main;
+    const STACK_SIZE: usize = 8 * 1024;
+    #[unsafe(link_section = ".bss.uninit")]
+    static mut STACK: [u8; STACK_SIZE] = [0; STACK_SIZE];
+    core::arch::naked_asm!(
+        // Disable interrupt
+        "csrw   mie, zero",
+        // Enable T-Head ISA extension
+        "li     t1, 1 << 22",
+        "csrs   0x7C0, t1",
+        // Enable T-Head caches
+        "li     t0, 0x70013
+        csrw    0x7C2, t0
+        li      t0, 0x11ff
+        csrw    0x7C1, t0
+        li      t0, 0x638000
+        csrs    0x7C0, t0
+        li      t0, 0x16e30c
+        csrw    0x7C5, t0",
+        // Invalidate instruction and data cache, branch history table
+        // and branch target buffer table
+        "li     t1, 0x30013",
+        "csrs   0x7C2, t1",
+        // Prepare programming language stack
+        "la     sp, {stack}
+        li      t0, {stack_size}
+        add     sp, sp, t0",
+        // Clear `.bss` section
+        "la     t1, sbss
+        la      t2, ebss
+    3:  bgeu    t1, t2, 3f
+        sd      zero, 0(t1)
+        addi    t1, t1, 8
+        j       3b
+    3:  ",
+        // Enable floating point unit
+        "call   {init_floating_point}",
+        // Start Rust main function
+        "call   {main}",
+        // Platform halt if main function returns
+    "3: wfi
+        j       3b",
+        stack      =   sym STACK,
+        stack_size = const STACK_SIZE,
+        init_floating_point = sym init_floating_point,
+        main       =   sym main,
+    )
+}

allwinner-rt/src/arch/riscv_fpu.rs

@@ -1,3 +1,5 @@
+use crate::start;
+
 /// eGON.BT0 identifying structure.
 // TODO verify with original ROM source code
 #[repr(C)]
@@ -27,3 +29,10 @@ static EGON_HEAD: EgonHead = EgonHead {
     boot_cpu: 0,
     platform: *b"\0\03.0.0\0",
 };
+
+core::arch::global_asm! {
+    ".section .text.head",
+    "head_jump:",
+    "j  {}",
+    sym start,
+}

allwinner-rt/src/arch/thead_c906.rs

@@ -28,104 +28,45 @@ pub use mctl::init as dram_init;
 
 pub use allwinner_rt_macros::entry;
 
+pub mod arch {
+    pub mod andes_a27l2;
+    pub mod riscv_fpu;
+    pub mod thead_c906;
+}
+
 pub mod soc {
     pub mod d1;
     pub mod v821;
     pub mod v853;
 }
 
-/// Jump over head data to executable code.
-///
-/// # Safety
-///
-/// Naked function.
-///
-/// NOTE: `mxstatus` is a custom T-Head register. Do not confuse with `mstatus`.
-/// It allows for configuring special eXtensions. See further below for details.
-#[unsafe(naked)]
-#[unsafe(link_section = ".text.entry")]
-unsafe extern "C" fn start() -> ! {
-    const STACK_SIZE: usize = 8 * 1024;
-    #[unsafe(link_section = ".bss.uninit")]
-    static mut STACK: [u8; STACK_SIZE] = [0; STACK_SIZE];
-    core::arch::naked_asm!(
-        // Disable interrupt
-        "csrw   mie, zero",
-        // Enable T-Head ISA extension
-        "li     t1, 1 << 22",
-        "csrs   0x7C0, t1",
-        // Enable T-Head caches
-        "li     t0, 0x70013
-        csrw    0x7C2, t0
-        li      t0, 0x11ff
-        csrw    0x7C1, t0
-        li      t0, 0x638000
-        csrs    0x7C0, t0
-        li      t0, 0x16e30c
-        csrw    0x7C5, t0",
-        // Invalidate instruction and data cache, branch history table
-        // and branch target buffer table
-        "li     t1, 0x30013",
-        "csrs   0x7C2, t1",
-        // Prepare programming language stack
-        "la     sp, {stack}
-        li      t0, {stack_size}
-        add     sp, sp, t0",
-        // Clear `.bss` section
-        "la     t1, sbss
-        la      t2, ebss
-    3:  bgeu    t1, t2, 3f
-        sd      zero, 0(t1)
-        addi    t1, t1, 8
-        j       3b
-    3:  ",
-        // Enable floating point unit
-        "li     t0, 0x4000",
-        "li     t1, 0x2000",
-        "csrrc  x0, mstatus, t0",
-        "csrrs  x0, mstatus, t1",
-        "fscsr  x0",
-        // Start Rust main function
-        "call   {main}",
-        // Platform halt if main function returns
-    "3: wfi
-        j       3b",
-        stack      =   sym STACK,
-        stack_size = const STACK_SIZE,
-        main       =   sym main,
-    )
-}
-
+#[allow(unused)]
 #[rustfmt::skip]
 unsafe extern "Rust" {
     // This symbol is generated by `#[entry]` macro in allwinner-rt or other ROM-stage software packages.
     fn main();
 }
 
-core::arch::global_asm! {
-    ".section .text.head",
-    "head_jump:",
-    "j  {}",
-    sym start,
-}
-
-#[cfg(feature = "d1")]
-pub use {
-    self::soc::d1::{__rom_init_params, Peripherals},
-    allwinner_hal::ccu::Clocks,
-};
-#[cfg(feature = "v821")]
-pub use {
-    self::soc::v821::{__rom_init_params, Peripherals},
-    allwinner_hal::ccu::Clocks,
-};
-
-#[cfg(not(any(feature = "d1", feature = "v821")))]
-pub struct Peripherals {}
-#[cfg(not(any(feature = "d1", feature = "v821")))]
-pub struct Clocks {}
-#[cfg(not(any(feature = "d1", feature = "v821")))]
-#[doc(hidden)]
-pub fn __rom_init_params() -> (Peripherals, Clocks) {
-    (Peripherals {}, Clocks {})
+cfg_if::cfg_if! {
+    if #[cfg(all(feature = "d1", target_arch = "riscv64"))] {
+        pub use {
+            self::arch::thead_c906::start,
+            self::soc::d1::{__rom_init_params, Peripherals},
+            allwinner_hal::ccu::Clocks,
+        };
+    } else if #[cfg(feature = "v821")] {
+        pub use {
+            self::arch::andes_a27l2::start,
+            self::soc::v821::{__rom_init_params, Peripherals},
+            allwinner_hal::ccu::Clocks,
+        };
+    } else {
+        pub struct Peripherals {}
+        pub struct Clocks {}
+        #[doc(hidden)]
+        pub fn __rom_init_params() -> (Peripherals, Clocks) {
+            (Peripherals {}, Clocks {})
+        }
+        pub fn start() {}
+    }
 }