Circular reasoning gates fail #1006
Description
an And gate cannot receive a signal from an Or gate fed by its output to keep it on?
I got past the first problem:
turns out it was reset by a short gap in the decade counter output. I added the capacitor.
now it fails because the Or gets startled when an input changes. Numbered by process order.
$ 1 5.0E-6 0.033846542510674225 50 5.0 50
152 512 224 608 224 0 2 0.0
150 512 96 608 96 0 2 0.0
w 512 208 608 96 0
w 608 176 608 224 0
w 608 96 624 96 0
163 128 368 256 368 0 10 0.0 0.0 0.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0
d 192 336 192 304 1 0.805904783
d 224 336 240 320 1 0.805904783
d 224 336 224 304 1 0.805904783
d 256 336 256 304 1 0.805904783
d 288 336 288 304 1 0.805904783
w 192 304 224 304 0
w 224 304 256 304 0
w 256 304 288 304 0
d 416 336 368 320 1 0.805904783
w 368 320 240 320 0
R 128 400 80 400 1 2 24999.999999999996 2.5 2.5 0.0 0.5
R 448 432 432 432 0 0 40.0 5.0 0.0 0.0 0.5
w 368 240 512 240 0
w 288 304 288 192 0
w 368 320 368 240 0
r 368 432 368 320 0 100.0
g 368 432 400 432 0
r 288 432 288 304 0 100.0
w 368 432 288 432 0
w 288 80 512 80 0
x 376 104 409 110 0 24 CS
x 409 246 453 252 0 24 ALE
150 512 288 608 288 0 2 0.0
w 624 96 624 256 0
w 624 256 512 256 0
w 512 304 448 304 0
I 368 320 448 320 0 0.5
x 546 294 559 300 0 24 3
x 546 230 559 236 0 24 2
x 552 104 565 110 0 24 1
w 512 256 512 272 0
w 512 80 656 80 0
I 656 288 656 112 0 0.5
150 656 96 752 96 0 2 0.0
x 696 102 709 108 0 24 4
w 656 288 608 288 0
I 288 192 496 192 0 0.5
w 288 80 288 192 0
d 320 336 320 304 1 0.805904783
w 288 304 320 304 0
x 546 356 559 362 0 24 5
w 496 192 496 368 0
w 784 96 752 96 0
x 742 126 775 132 0 24 CS
150 512 352 608 352 0 2 0.0
w 512 368 496 368 0
w 448 304 448 320 0
w 512 336 512 320 0
w 512 320 624 320 0
w 624 320 624 256 0
w 512 160 512 112 0
w 608 352 640 352 0
I 640 352 640 144 0 0.5
150 608 160 512 160 0 2 0.0
w 608 144 640 144 0
x 549 166 562 172 0 24 6
c 256 192 256 224 0 1.0000000000000001E-7 4.264990205724156
g 256 224 256 240 0
w 256 192 288 192 0