Cadence OSPI + Infineon SEMPER flash changes #1
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Add a Cadence MSPI peripheral driver, used in the TI K3 platform. The driver was tested in 1S-1S-1S and 4S-4S-4S mode with the onboard infineon s25h flash of the am243x launchpad and a custom driver for the flash using this interface. The command and dummy cycles are always taken from the xfer request and never from the devicetree since different commands might have different latencies. The driver is somewhat basic for now and lacks e.g. callback implementation. This is something that can be added in the future. If a non-supported / invalid request is detected a error code is returned. Signed-off-by: Mika Braunschweig <[email protected]>
Add a infineon s25h mspi nor flash driver. This driver was tested on the am243x-lp board. It assumes the flash is in 1S-1S-1S mode and sends a reset command. After that it disables the uniform hybrid sector architecture, if activated, and applies the setting by resetting the flash again. After that the 4S-4S-4S mode is entered and also 4 byte adressing gets enabled. During these stepts the JEDEC id is sometimes verified to ensure a valid connection. Due to the flash possibily entering continious read mode when undesired some read operations will read the JEDEC id to prevent this. Signed-off-by: Mika Braunschweig <[email protected]>
Cadence OSPI controller allows dual byte opcodes which are used by the flash on the bus for modes such as Octal SDR/DDR. Hence, allow configuration for dual byte opcodes. Signed-off-by: Amneesh Singh <[email protected]>
Cadence OSPI/QSPI controller allows peripherals on its bus to have configurations like 8D-8D-8D or 4S-4D-4D which require DTR configuration for dual transfer rate. Hence, allow having DTR configuration in the driver. Signed-off-by: Amneesh Singh <[email protected]>
We configure address length as 'length - 1' in the controller. This currently does not check if the length is 0, in which case it causes unsigned integer underflow, so add a check for that. Signed-off-by: Amneesh Singh <[email protected]>
For indirect read/write operations, data is transferred using a FIFO in the flash region by the controller. Currently this is configured to be at offset 0 i.e, at the start of the flash region. The user might want to change the offset to something else for a variety of reasons, and hence, allow configuring this region by modifying the following DT properties. - 'reg' property at index 1 now contains the base address for the flash region. - 'indirect-trigger-offset' property is used to set the offset for the FIFO making the absolute address for the fifo as the sum of this value and the aforementioned address. The reason we need both these properties is that, we need the offset for configuring the controller register and the absolute address (sum) for host access. Signed-off-by: Amneesh Singh <[email protected]>
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This PR exists just for discussion and cherrypicking and if convenient, merging purposes for the upstream PR support. See individual commit messages for descriptions.