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scripts: add Cadence QSPI-NOR registers
Adds register definitions for Cadence QSPI-NOR controllers.
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‎generate_svd.py

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@@ -13,6 +13,7 @@
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import inspect
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import pydevicetree
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from scripts.arm_pl022 import generate_registers_arm_pl022
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from scripts.cdns_qspi_nor import generate_registers_cdns_qspi
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from scripts.riscv_clint0_control import generate_registers_riscv_clint0
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from scripts.sifive_clic0_control import generate_registers_sifive_clic0
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from scripts.riscv_plic0_control import generate_registers_riscv_plic0
@@ -174,6 +175,8 @@ def generate_peripheral(dts, peripheral, comp, ext, reg, regmap_path):
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if regmap_path.endswith("arm_pl022.py"):
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name = "spi{}".format(ext)
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elif regmap_path.endswith("cdns_qspi_nor.py"):
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name = "qspi".format(ext)
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elif regmap_path.endswith("riscv_clint0_control.py"):
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name = "clint"
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elif regmap_path.endswith("riscv_plic0_control.py"):
@@ -231,6 +234,8 @@ def generate_registers(dts, peripheral, regmap_path):
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"""Generate xml string for registers from regmap file or generator code"""
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if regmap_path.endswith("arm_pl022.py"):
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return generate_registers_arm_pl022(dts, peripheral)
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if regmap_path.endswith("cdns_qspi_nor.py"):
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return generate_registers_cdns_qspi(dts, peripheral)
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if regmap_path.endswith("riscv_clint0_control.py"):
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return generate_registers_riscv_clint0(dts)
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if regmap_path.endswith("sifive_clic0_control.py"):

‎scripts/cdns_qspi_nor.py

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@@ -0,0 +1,198 @@
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#!/usr/bin/env python3
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# Copyleft (c) 2023 cmsis-svd-generator developers
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# SPDX-License-Identifier: Apache-2.0
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from scripts.starfive_common import *
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"""
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This program generates CMSIS SVD xml for cadence QSPI
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"""
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def generate_registers_cdns_qspi(dts, peripheral):
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"""Generate xml string for registers for cadence_qspi peripheral"""
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txt = """\
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<registers>
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"""
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txt += generate_register("config", "Cadence QSPI Configuration", 0x00, [
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("enable", "Enable the QSPI controller", "[0:0]", "read-write"),
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("enb_dir_acc_ctrl", "Enable direct access controller", "[7:7]", "read-write"),
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("decode", "Enable the QSPI decoder", "[9:9]", "read-write"),
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("chipselect", "Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111", "[13:10]", "read-write"),
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("dma", "Enable Direct Memory Access", "[15:15]", "read-write"),
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("baud", "Set the QSPI BAUD rate divisor", "[22:19]", "read-write"),
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("dtr_proto", "Enable DTR Protocol", "[24:24]", "read-write"),
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("dual_opcode", "Enable Dual Opcode Mode", "[30:30]", "read-write"),
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("idle", "Set Idle", "[31:31]", "read-write"),
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])
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txt += generate_register("rd_instr", "Cadence QSPI Read Instruction", 0x04, [
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("opcode", "Instruction Opcode", "[7:0]", "read-write"),
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("type_instr", "Type of Instruction", "[9:8]", "read-write"),
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("type_addr", "Type of Address", "[13:12]", "read-write"),
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("type_data", "", "[17:16]", "read-write"),
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("mode_en", "Mode ", "[20:20]", "read-write"),
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("dummy", "Send dummy signal to stall the device", "[28:24]", "read-write"),
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])
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txt += generate_register("wr_instr", "Cadence QSPI Write Instruction", 0x08, [
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("opcode", "Instruction Opcode", "[7:0]", "read-write"),
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("type_addr", "Type of Address", "[13:12]", "read-write"),
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("type_data", "", "[17:16]", "read-write"),
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])
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txt += generate_register("delay", "Cadence QSPI Delay", 0x0c, [
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("tslch", "TSLCH Delay Value", "[7:0]", "read-write"),
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("tchsh", "TCHSH Delay Value", "[15:8]", "read-write"),
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("tsd2d", "TSD2D Delay Value", "[23:16]", "read-write"),
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("tshsl", "TSHSL Delay Value", "[31:24]", "read-write"),
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])
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txt += generate_register("read_capture", "Cadence QSPI Read Capture", 0x10, [
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("bypass", "Bypass the Read Capture", "[0:0]", "read-write"),
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("delay", "Read Capture Delay Value", "[4:1]", "read-write"),
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])
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txt += generate_register("size", "Cadence QSPI Size Configuration", 0x14, [
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("address", "Address Size in Bytes", "[3:0]", "read-write"),
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("page", "Page Size in Bytes", "[15:4]", "read-write"),
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("block", "Block Size in Bytes", "[21:16]", "read-write"),
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])
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txt += generate_register("sram_partition", "Cadence QSPI SRAM Partition Size", 0x18, [
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("size", "Partition size in bytes", "[31:0]", "read-write"),
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])
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txt += generate_register("indirect_trigger", "Cadence QSPI Indirect Trigger Address", 0x1c, [
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("address", "", "[31:0]", "read-write"),
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])
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txt += generate_register("dma", "Cadence QSPI Direct Memory Access", 0x20, [
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("single", "", "[7:0]", "read-write"),
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("burst", "", "[15:8]", "read-write"),
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])
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txt += generate_register("remap", "Cadence QSPI Remap Address", 0x24, [
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("address", "", "[31:0]", "read-write"),
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])
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txt += generate_register("mode_bit", "Cadence QSPI Mode Bit(s)", 0x28, [
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("mode", "", "[31:0]", "read-write"),
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])
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txt += generate_register("sdram_level", "Cadence QSPI SDRAM Level", 0x2c, [
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("rd", "SDRAM Read Level", "[15:0]", "read-only"),
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("wr", "SDRAM Write Level", "[31:16]", "read-only"),
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])
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txt += generate_register("wr_completion_ctrl", "Cadence QSPI Write Completion Control", 0x38, [
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# FIXME: fill out the remaining control fields. This is the only field in the Linux driver.
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("disable_auto_poll", "SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register.", "[14:14]", "read-write"),
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])
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txt += generate_register("irq_status", "Cadence QSPI IRQ Status", 0x40, [
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("mode_err", "Mode error interrupt", "[0:0]", "read-write"),
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("underflow", "Buffer underflow interrupt", "[1:1]", "read-write"),
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("ind_comp", "Indirect computation interrupt", "[2:2]", "read-write"),
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("ind_rd_reject", "Indirect read rejection interrupt", "[3:3]", "read-write"),
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("wr_protected_err", "Write protected error interrupt", "[4:4]", "read-write"),
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("illegal_ahb_err", "Illegal AHB clock error interrupt", "[5:5]", "read-write"),
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("watermark", "Watermark interrupt", "[6:6]", "read-write"),
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("ind_sram_full", "Indirect SRAM full interrupt", "[12:12]", "read-write"),
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# Reset value: (0b1_1111_1111_1111)
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], 32, 0x1ffff)
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txt += generate_register("irq_mask", "Cadence QSPI IRQ Mask", 0x44, [
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("mode_err", "Mode error interrupt", "[0:0]", "read-write"),
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("underflow", "Buffer underflow interrupt", "[1:1]", "read-write"),
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("ind_comp", "Indirect computation interrupt", "[2:2]", "read-write"),
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("ind_rd_reject", "Indirect read rejection interrupt", "[3:3]", "read-write"),
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("wr_protected_err", "Write protected error interrupt", "[4:4]", "read-write"),
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("illegal_ahb_err", "Illegal AHB clock error interrupt", "[5:5]", "read-write"),
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("watermark", "Watermark interrupt", "[6:6]", "read-write"),
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("ind_sram_full", "Indirect SRAM full interrupt", "[12:12]", "read-write"),
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# Reset value: (IND_COMP | WATERMARK | UNDERFLOW)
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], 32, 0x46)
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txt += generate_register("indirect_rd", "Cadence QSPI Indirect Read", 0x60, [
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("start", "Start indirect read", "[0:0]", "read-write"),
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("cancel", "Cancel indirect read", "[1:1]", "read-write"),
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("done", "Indirect read done", "[5:5]", "read-write"),
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])
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txt += generate_register("indirect_rd_watermark", "Cadence QSPI Indirect Read Watermark", 0x64, [
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("watermark", "", "[31:0]", "read-write"),
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])
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txt += generate_register("indirect_rd_start_addr", "Cadence QSPI Indirect Read Start Address", 0x68, [
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("address", "", "[31:0]", "read-write"),
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])
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txt += generate_register("indirect_rd_bytes", "Cadence QSPI Indirect Read Bytes", 0x6c, [
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("bytes", "", "[31:0]", "read-write"),
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])
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txt += generate_register("indirect_wr", "Cadence QSPI Indirect Write", 0x70, [
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("start", "Start indirect write", "[0:0]", "read-write"),
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("cancel", "Cancel indirect write", "[1:1]", "read-write"),
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("done", "Indirect write done", "[5:5]", "read-write"),
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])
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txt += generate_register("indirect_wr_watermark", "Cadence QSPI Indirect Write Watermark", 0x74, [
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("watermark", "", "[31:0]", "read-write"),
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])
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txt += generate_register("indirect_wr_start_addr", "Cadence QSPI Indirect Write Start Address", 0x78, [
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("address", "", "[31:0]", "read-write"),
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])
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txt += generate_register("indirect_wr_bytes", "Cadence QSPI Indirect Write Bytes", 0x7c, [
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("bytes", "", "[31:0]", "read-write"),
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])
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txt += generate_register("cmd_ctrl", "Cadence QSPI Command Control", 0x90, [
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("execute", "Execute-in-Place (XIP)", "[0:0]", "read-write"),
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("in_progress", "Command in progress", "[1:1]", "read-write"),
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("dummy", "Dummy command", "[11:7]", "read-write"),
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("wr_bytes", "Write bytes", "[14:12]", "read-write"),
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("wr_en", "Write enable", "[15:15]", "read-write"),
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("add_bytes", "Add command bytes", "[17:16]", "read-write"),
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("addr_en", "Address enable", "[19:19]", "read-write"),
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("rd_bytes", "Read bytes", "[22:20]", "read-write"),
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("rd_en", "Read enable", "[23:23]", "read-write"),
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("opcode", "Command opcode", "[31:24]", "read-write"),
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])
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txt += generate_register("cmd_address", "Cadence QSPI Command Address", 0x94, [
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("address", "", "[31:0]", "read-write"),
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])
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txt += generate_register("cmd_read_at_lower", "Cadence QSPI Command Read at Lower", 0xa0, [
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("read_at_lower", "", "[31:0]", "read-write"),
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])
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txt += generate_register("cmd_read_at_upper", "Cadence QSPI Command Read at Upper", 0xa4, [
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("read_at_upper", "", "[31:0]", "read-write"),
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])
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txt += generate_register("cmd_write_at_lower", "Cadence QSPI Command Write at Lower", 0xa8, [
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("write_at_lower", "", "[31:0]", "read-write"),
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])
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txt += generate_register("cmd_write_at_upper", "Cadence QSPI Command Write at Upper", 0xac, [
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("write_at_upper", "", "[31:0]", "read-write"),
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])
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txt += generate_register("polling_status", "Cadence QSPI Polling Status", 0xb0, [
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("status", "", "[15:0]", "read-write"),
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("dummy", "", "[20:16]", "read-write"),
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])
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txt += generate_register("ext_lower", "Cadence QSPI Extension Lower", 0xe0, [
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("stig", "", "[15:0]", "read-write"),
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("write", "", "[23:16]", "read-write"),
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("read", "", "[31:24]", "read-write"),
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])
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return txt + """\
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</registers>
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"""

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