feature: scripts: add JH7110 DMC peripherals

Adds function to generate register arrays using the `dim` and
`dimIncrement` register attributes.

Adds scripts to generate JH7110 DDR memory controller CTRL and PHY
peripheral registers.

Author: rmsyn

generate_svd.py

@@ -20,6 +20,8 @@
 from scripts.snps_designware_i2c import generate_registers_snps_designware_i2c
 from scripts.snps_dw_apb_uart import generate_registers_snps_dw_apb_uart
 from scripts.starfive_common import generate_interrupt
+from scripts.starfive_jh7110_dmc_ctrl import generate_registers_starfive_jh7110_dmc_ctrl
+from scripts.starfive_jh7110_dmc_phy import generate_registers_starfive_jh7110_dmc_phy
 from scripts.starfive_jh7110_pmu import generate_registers_starfive_jh7110_pmu
 from scripts.starfive_jh7110_stgcrg import generate_registers_starfive_jh7110_stgcrg
 from scripts.starfive_jh7110_syscrg import generate_registers_starfive_jh7110_syscrg
@@ -124,13 +126,13 @@ def generate_peripherals(dts):
 
                     if "clint" in comp and not os.path.exists(script_path):
                         regmap_path = ""
-                        script_path = os.path.join(regmap_root, "scripts", "riscv_clint0_control.py") 
+                        script_path = os.path.join(regmap_root, "scripts", "riscv_clint0_control.py")
                     elif "plic" in comp and not os.path.exists(script_path):
                         regmap_path = ""
-                        script_path = os.path.join(regmap_root, "scripts", "riscv_plic0_control.py") 
+                        script_path = os.path.join(regmap_root, "scripts", "riscv_plic0_control.py")
                     elif "clic" in comp and not os.path.exists(script_path):
                         regmap_path = ""
-                        script_path = os.path.join(regmap_root, "scripts", "sifive_clic0_control.py") 
+                        script_path = os.path.join(regmap_root, "scripts", "sifive_clic0_control.py")
 
                     if os.path.exists(regmap_path):
                         ext = str(idx[comp])
@@ -211,6 +213,10 @@ def generate_peripheral(dts, peripheral, comp, ext, reg, regmap_path):
         name = "pwm"
     elif regmap_path.endswith("starfive_jh7110_trng.py"):
         name = "trng"
+    elif regmap_path.endswith("starfive_jh7110_dmc_ctrl.py"):
+        name = "dmc_ctrl"
+    elif regmap_path.endswith("starfive_jh7110_dmc_phy.py"):
+        name = "dmc_phy"
     else:
         name = "{}_{}".format(get_name_as_id(comp), ext)
 
@@ -251,6 +257,10 @@ def generate_registers(dts, peripheral, regmap_path):
         return generate_registers_snps_designware_i2c(dts, peripheral)
     if regmap_path.endswith("snps_dw_apb_uart.py"):
         return generate_registers_snps_dw_apb_uart(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_dmc_ctrl.py"):
+        return generate_registers_starfive_jh7110_dmc_ctrl(dts, peripheral)
+    if regmap_path.endswith("starfive_jh7110_dmc_phy.py"):
+        return generate_registers_starfive_jh7110_dmc_phy(dts, peripheral)
     if regmap_path.endswith("starfive_jh7110_pmu.py"):
         return generate_registers_starfive_jh7110_pmu(dts, peripheral)
     if regmap_path.endswith("starfive_jh7110_syscrg.py"):

scripts/starfive_common.py

@@ -230,6 +230,18 @@ def generate_register(name, desc, addr, field_name_desc_range_access, size=32, r
                 </register>
 """
 
+def generate_register_arr(name, desc, addr, dim, dim_inc, reset_value=0):
+    return """\
+                <register>
+                  <dim>""" + str(dim) + """</dim>
+                  <dimIncrement>""" + "{:#x}".format(dim_inc) + """</dimIncrement>
+                  <name>""" + name + """[%s]</name>
+                  <description>""" + desc + """</description>
+                  <addressOffset>""" + "{:#x}".format(addr) + """</addressOffset>
+                  <resetValue>""" + str(reset_value) + """</resetValue>
+                </register>
+"""
+
 def generate_field(name, desc, bit_range, access):
     if len(desc) == 0:
         desc = name

scripts/starfive_jh7110_dmc_ctrl.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# Copyleft (c) 2023 cmsis-svd-generator developers
+# SPDX-License-Identifier: Apache-2.0
+
+from scripts.starfive_common import *
+
+"""
+This program generates CMSIS SVD xml for starfive JH7110 dmc ctrl
+"""
+
+def generate_registers_starfive_jh7110_dmc_ctrl(dts, peripheral):
+    """Generate xml string for registers for starfive_dmc_ctrl peripheral"""
+    txt = """\
+              <registers>
+"""
+
+    txt += generate_register_arr("csr", "DDR Memory Control CSR register", 0x0, 1024, 0x20)
+    txt += generate_register_arr("sec", "DDR Memory Control SEC register", 0x1000, 1024, 0x20)
+
+    return txt + """\
+              </registers>
+"""

scripts/starfive_jh7110_dmc_phy.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# Copyleft (c) 2023 cmsis-svd-generator developers
+# SPDX-License-Identifier: Apache-2.0
+
+from scripts.starfive_common import *
+
+"""
+This program generates CMSIS SVD xml for starfive JH7110 dmc phy
+"""
+
+def generate_registers_starfive_jh7110_dmc_phy(dts, peripheral):
+    """Generate xml string for registers for starfive_dmc_phy peripheral"""
+    txt = """\
+              <registers>
+"""
+
+    txt += generate_register_arr("csr", "DDR Memory Control PHY CSR", 0x0, 512, 0x20)
+    txt += generate_register_arr("base", "DDR Memory Control PHY Base register", 0x800, 512, 0x20)
+    txt += generate_register_arr("ac_base", "DDR Memory Control PHY AC Base register", 0x1000, 512, 0x20)
+
+    return txt + """\
+              </registers>
+"""