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Ruhungmr-c
Ruhung
authored and
mr-c
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[NEON] Fix mvn.h to correctly handle RVV instructions.
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‎simde/arm/neon/mvn.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ simde_vmvnq_s8(simde_int8x16_t a) {
5858
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
5959
r_.values = ~a_.values;
6060
#elif defined(SIMDE_RISCV_V_NATIVE)
61-
r_.sv128 = __riscv_vnot_v_i8m1(a_.sv128, b_.sv128, 16);
61+
r_.sv128 = __riscv_vnot_v_i8m1(a_.sv128, 16);
6262
#else
6363
SIMDE_VECTORIZE
6464
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -95,7 +95,7 @@ simde_vmvnq_s16(simde_int16x8_t a) {
9595
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
9696
r_.values = ~a_.values;
9797
#elif defined(SIMDE_RISCV_V_NATIVE)
98-
r_.sv128 = __riscv_vnot_v_i16m1(a_.sv128, b_.sv128, 8);
98+
r_.sv128 = __riscv_vnot_v_i16m1(a_.sv128, 8);
9999
#else
100100
SIMDE_VECTORIZE
101101
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -132,7 +132,7 @@ simde_vmvnq_s32(simde_int32x4_t a) {
132132
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
133133
r_.values = ~a_.values;
134134
#elif defined(SIMDE_RISCV_V_NATIVE)
135-
r_.sv128 = __riscv_vnot_v_i32m1(a_.sv128, b_.sv128, 4);
135+
r_.sv128 = __riscv_vnot_v_i32m1(a_.sv128, 4);
136136
#else
137137
SIMDE_VECTORIZE
138138
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -169,7 +169,7 @@ simde_vmvnq_u8(simde_uint8x16_t a) {
169169
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
170170
r_.values = ~a_.values;
171171
#elif defined(SIMDE_RISCV_V_NATIVE)
172-
r_.sv128 = __riscv_vnot_v_u8m1(a_.sv128, b_.sv128, 16);
172+
r_.sv128 = __riscv_vnot_v_u8m1(a_.sv128, 16);
173173
#else
174174
SIMDE_VECTORIZE
175175
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -206,7 +206,7 @@ simde_vmvnq_u16(simde_uint16x8_t a) {
206206
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
207207
r_.values = ~a_.values;
208208
#elif defined(SIMDE_RISCV_V_NATIVE)
209-
r_.sv128 = __riscv_vnot_v_u16m1(a_.sv128, b_.sv128, 8);
209+
r_.sv128 = __riscv_vnot_v_u16m1(a_.sv128, 8);
210210
#else
211211
SIMDE_VECTORIZE
212212
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -243,7 +243,7 @@ simde_vmvnq_u32(simde_uint32x4_t a) {
243243
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
244244
r_.values = ~a_.values;
245245
#elif defined(SIMDE_RISCV_V_NATIVE)
246-
r_.sv128 = __riscv_vnot_v_u32m1(a_.sv128, b_.sv128, 4);
246+
r_.sv128 = __riscv_vnot_v_u32m1(a_.sv128, 4);
247247
#else
248248
SIMDE_VECTORIZE
249249
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -274,7 +274,7 @@ simde_vmvn_s8(simde_int8x8_t a) {
274274
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
275275
r_.values = ~a_.values;
276276
#elif defined(SIMDE_RISCV_V_NATIVE)
277-
r_.sv64 = __riscv_vnot_v_i8m1(a_.sv64, b_.sv64, 8);
277+
r_.sv64 = __riscv_vnot_v_i8m1(a_.sv64, 8);
278278
#else
279279
SIMDE_VECTORIZE
280280
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -305,7 +305,7 @@ simde_vmvn_s16(simde_int16x4_t a) {
305305
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
306306
r_.values = ~a_.values;
307307
#elif defined(SIMDE_RISCV_V_NATIVE)
308-
r_.sv64 = __riscv_vnot_v_i16m1(a_.sv64, b_.sv64, 4);
308+
r_.sv64 = __riscv_vnot_v_i16m1(a_.sv64, 4);
309309
#else
310310
SIMDE_VECTORIZE
311311
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -336,7 +336,7 @@ simde_vmvn_s32(simde_int32x2_t a) {
336336
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
337337
r_.values = ~a_.values;
338338
#elif defined(SIMDE_RISCV_V_NATIVE)
339-
r_.sv64 = __riscv_vnot_v_i32m1(a_.sv64, b_.sv64, 2);
339+
r_.sv64 = __riscv_vnot_v_i32m1(a_.sv64, 2);
340340
#else
341341
SIMDE_VECTORIZE
342342
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -367,7 +367,7 @@ simde_vmvn_u8(simde_uint8x8_t a) {
367367
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
368368
r_.values = ~a_.values;
369369
#elif defined(SIMDE_RISCV_V_NATIVE)
370-
r_.sv64 = __riscv_vnot_v_u8m1(a_.sv64, b_.sv64, 8);
370+
r_.sv64 = __riscv_vnot_v_u8m1(a_.sv64, 8);
371371
#else
372372
SIMDE_VECTORIZE
373373
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -398,7 +398,7 @@ simde_vmvn_u16(simde_uint16x4_t a) {
398398
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
399399
r_.values = ~a_.values;
400400
#elif defined(SIMDE_RISCV_V_NATIVE)
401-
r_.sv64 = __riscv_vnot_v_u16m1(a_.sv64, b_.sv64, 4);
401+
r_.sv64 = __riscv_vnot_v_u16m1(a_.sv64, 4);
402402
#else
403403
SIMDE_VECTORIZE
404404
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
@@ -429,7 +429,7 @@ simde_vmvn_u32(simde_uint32x2_t a) {
429429
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
430430
r_.values = ~a_.values;
431431
#elif defined(SIMDE_RISCV_V_NATIVE)
432-
r_.sv64 = __riscv_vnot_v_u32m1(a_.sv64, b_.sv64, 2);
432+
r_.sv64 = __riscv_vnot_v_u32m1(a_.sv64, 2);
433433
#else
434434
SIMDE_VECTORIZE
435435
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {

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