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‎cla.rca/hdl/BitMux21.v

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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//-- The Free IP Project
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//-- Verilog Free-CORDIC Core
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//-- (c) 2000, The Free IP Project and Rohit Sharma ([email protected])
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//--
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//--
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//-- FREE IP GENERAL PUBLIC LICENSE
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//-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
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//--
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//-- 1. You may copy and distribute verbatim copies of this core, as long
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//-- as this file, and the other associated files, remain intact and
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//-- unmodified. Modifications are outlined below.
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//-- 2. You may use this core in any way, be it academic, commercial, or
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//-- military. Modified or not.
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//-- 3. Distribution of this core must be free of charge. Charging is
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//-- allowed only for value added services. Value added services
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//-- would include copying fees, modifications, customizations, and
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//-- inclusion in other products.
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//-- 4. If a modified source code is distributed, the original unmodified
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//-- source code must also be included (or a link to the Free IP web
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//-- site). In the modified source code there must be clear
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//-- identification of the modified version.
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//-- 5. Visit the Free IP web site for additional information.
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//-- http://www.free-ip.com
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//--
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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module BitMux2_1 (out,a,b,select);
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output out;
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input a,b,select;
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reg out;
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always @ (select or a or b)
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case (select)
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1'b0: out <= a;
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1'b1: out <= b;
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default: out <= b;
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endcase
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endmodule //BitMux2_1
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‎cla.rca/hdl/BusMux21.v

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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//-- The Free IP Project
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//-- Verilog Free-CORDIC Core
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//-- (c) 2000, The Free IP Project and Rohit Sharma ([email protected])
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//--
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//--
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//-- FREE IP GENERAL PUBLIC LICENSE
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//-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
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//--
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//-- 1. You may copy and distribute verbatim copies of this core, as long
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//-- as this file, and the other associated files, remain intact and
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//-- unmodified. Modifications are outlined below.
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//-- 2. You may use this core in any way, be it academic, commercial, or
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//-- military. Modified or not.
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//-- 3. Distribution of this core must be free of charge. Charging is
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//-- allowed only for value added services. Value added services
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//-- would include copying fees, modifications, customizations, and
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//-- inclusion in other products.
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//-- 4. If a modified source code is distributed, the original unmodified
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//-- source code must also be included (or a link to the Free IP web
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//-- site). In the modified source code there must be clear
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//-- identification of the modified version.
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//-- 5. Visit the Free IP web site for additional information.
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//-- http://www.free-ip.com
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//--
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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module BusMux2_1(out,data0,data1,select);
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output [`REG_SIZE:0] out;
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input [`REG_SIZE:0] data0,data1;
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input select;
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reg [`REG_SIZE:0] out;
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always @ (select or data0 or data1)
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case (select)
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1'b0: out <= data0;
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1'b1: out <= data1;
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default: out <= data1;
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endcase
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endmodule //Mux2_1 delay : delay of BitMux2_1
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‎cla.rca/hdl/adder.v

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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//-- The Free IP Project
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//-- Verilog Free-CORDIC Core
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//-- (c) 2000, The Free IP Project and Rohit Sharma ([email protected])
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//--
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//--
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//-- FREE IP GENERAL PUBLIC LICENSE
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//-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
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//--
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//-- 1. You may copy and distribute verbatim copies of this core, as long
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//-- as this file, and the other associated files, remain intact and
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//-- unmodified. Modifications are outlined below.
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//-- 2. You may use this core in any way, be it academic, commercial, or
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//-- military. Modified or not.
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//-- 3. Distribution of this core must be free of charge. Charging is
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//-- allowed only for value added services. Value added services
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//-- would include copying fees, modifications, customizations, and
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//-- inclusion in other products.
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//-- 4. If a modified source code is distributed, the original unmodified
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//-- source code must also be included (or a link to the Free IP web
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//-- site). In the modified source code there must be clear
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//-- identification of the modified version.
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//-- 5. Visit the Free IP web site for additional information.
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//-- http://www.free-ip.com
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//--
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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/********************************Test Case ***************
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`include "header.v"
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`include "cla.v"
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`include "BusMux21.v"
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`include "compl.v"
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module test ;
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reg [`REG_SIZE:0] A, B;
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reg Asgn, AS;
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wire [`REG_SIZE:0] S;
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Adder testit ( S, sgn, Asgn, A, B, AS ) ;
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initial
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begin
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AS <= 0; Asgn <= 0 ;
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A <= 12; B<= 65534 ;
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$stop ;
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$monitor ( "Sum=%d sign=%d ASign=%b A=%d B=%d AS=%d", S, sgn, Asgn, A, B, AS ) ;
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end
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endmodule
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********************************Test Case ***************/
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module Adder (S, sign, Asign, A, B, AS);
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output [`REG_SIZE:0] S;
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output sign;
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input [`REG_SIZE:0] A,B;
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input Asign,AS;
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wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;
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reg [`REG_SIZE:0] CIN;
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wire Y_1,Y_2,Y_3,Y_4;
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assign Y_1 = (~AS) & Asign;
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BusMux2_1 MUX_0 (Atemp,A,B,Y_1); // xchange A & B
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BusMux2_1 MUX_1 (Btemp,B,A,Y_1);
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assign Y_2 = Asign ^ AS;
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integer i;
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always @ (Y_2)
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begin
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for(i=0;i<`REG_SIZE+1;i=i+1)
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CIN[i] <= Y_2;
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end
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assign Btemp1 = Btemp ^ CIN;
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CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);
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CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);
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CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);
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CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);
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assign Y_4 = (~Y_3) & (Asign ^ AS);
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complement Compl (S,Stemp,Y_4); // 2's Complement if result neg.
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assign sign = (~Y_3 & AS) | (~Y_3 & Asign) | (AS & Asign);
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endmodule // Adder

‎cla.rca/hdl/cla.v

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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//-- The Free IP Project
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//-- Verilog Free-CORDIC Core
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//-- (c) 2000, The Free IP Project and Rohit Sharma ([email protected])
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//--
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//--
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//-- FREE IP GENERAL PUBLIC LICENSE
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//-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
11+
//--
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//-- 1. You may copy and distribute verbatim copies of this core, as long
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//-- as this file, and the other associated files, remain intact and
14+
//-- unmodified. Modifications are outlined below.
15+
//-- 2. You may use this core in any way, be it academic, commercial, or
16+
//-- military. Modified or not.
17+
//-- 3. Distribution of this core must be free of charge. Charging is
18+
//-- allowed only for value added services. Value added services
19+
//-- would include copying fees, modifications, customizations, and
20+
//-- inclusion in other products.
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//-- 4. If a modified source code is distributed, the original unmodified
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//-- source code must also be included (or a link to the Free IP web
23+
//-- site). In the modified source code there must be clear
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//-- identification of the modified version.
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//-- 5. Visit the Free IP web site for additional information.
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//-- http://www.free-ip.com
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//--
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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/********************************Test Case ***************
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module test ;
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reg [`CLA_SIZE:0] A, B;
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reg CI;
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wire [`CLA_SIZE:0] S;
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CLA testit ( S, CO, A, B, CI );
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initial
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begin
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CI <= 0;
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A <= 12; B<= 4095 ;
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$monitor ( "CI=%d A=%d B=%d S=%d CO=%d",CI,A,B,S,CO);
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end
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endmodule
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********************************Test Case ***************/
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module CLA ( s, co, a, b, ci );
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input ci;
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input [`CLA_SIZE:0] a, b;
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output [`CLA_SIZE:0] s;
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output co;
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reg [`CLA_SIZE:0] carrychain;
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integer i;
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wire [`CLA_SIZE:0] p = a ^ b;
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wire [`CLA_SIZE:0] g = a & b;
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wire [`CLA_SIZE+1:0] shiftedcarry = {carrychain, ci};
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wire [`CLA_SIZE:0] s = p ^ shiftedcarry[`CLA_SIZE:0];
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wire co = shiftedcarry[`CLA_SIZE+1];
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always @ (a or b or ci or g or p)
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begin
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carrychain[0] = g[0] | (p[0] & ci);
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for ( i = 1; i <= `CLA_SIZE; i = i + 1)
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carrychain[i] = g[i] | (p[i] & carrychain[i-1]);
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end
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endmodule
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‎cla.rca/hdl/compl.v

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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//-- The Free IP Project
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//-- Verilog Free-CORDIC Core
6+
//-- (c) 2000, The Free IP Project and Rohit Sharma ([email protected])
7+
//--
8+
//--
9+
//-- FREE IP GENERAL PUBLIC LICENSE
10+
//-- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
11+
//--
12+
//-- 1. You may copy and distribute verbatim copies of this core, as long
13+
//-- as this file, and the other associated files, remain intact and
14+
//-- unmodified. Modifications are outlined below.
15+
//-- 2. You may use this core in any way, be it academic, commercial, or
16+
//-- military. Modified or not.
17+
//-- 3. Distribution of this core must be free of charge. Charging is
18+
//-- allowed only for value added services. Value added services
19+
//-- would include copying fees, modifications, customizations, and
20+
//-- inclusion in other products.
21+
//-- 4. If a modified source code is distributed, the original unmodified
22+
//-- source code must also be included (or a link to the Free IP web
23+
//-- site). In the modified source code there must be clear
24+
//-- identification of the modified version.
25+
//-- 5. Visit the Free IP web site for additional information.
26+
//-- http://www.free-ip.com
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//--
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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/************************Test Case *****************
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module test ;
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reg [`REG_SIZE:0] datain ;
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wire [`REG_SIZE:0] dataout ;
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reg enable ;
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initial
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begin
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enable = 1 ;
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datain = 12'b110011001100;
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$monitor ( "datain = %b \t dataout = %b", datain, dataout );
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#10 enable = 0 ;
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$display ( "datain = %b \t dataout = %b", datain, dataout );
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end
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complement testc (dataout, datain, enable);
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endmodule
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************************Test Case *****************/
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module complement (dataout, datain, enable);
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output [`REG_SIZE:0] dataout;
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input [`REG_SIZE:0] datain;
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input enable;
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reg [`REG_SIZE:0] Co, dataout, Enable;
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reg Cin;
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integer i,j;
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always @ (enable)
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begin
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for(j=0;j<`REG_SIZE+1;j=j+1)
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Enable[j] = enable;
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end
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wire [`REG_SIZE:0] A = datain ^ Enable;
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always @ (enable)
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begin
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case (enable)
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1'b0: Cin <= 1'b0;
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1'b1: Cin <= 1'b1;
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default: Cin <= 1'b1;
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endcase
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end
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always @ (A or Cin )
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begin
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dataout[0] = A[0] ^ Cin;
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Co[0] = A[0] & Cin;
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for(i = 1; i <=`REG_SIZE; i = i + 1)
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begin
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dataout[i] = A[i] ^ Co[i-1];
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Co[i] = A[i] & Co[i-1];
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end
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end
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endmodule // 2compl delay : BitMux2_1 delay + 12 * HA1 dalay
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