PLL2 and PLL3 on STM32F107

[unsanded]

related to #448
Stm32f107 has 3 plls in the clock system. My board uses a 25MHz crystal, so the only way to get to a round 72MHz SYSCLK is to do: 25 / 5 * 8 / 5 * 9 (see the screenshot from cubeMX.

The PLL3 is not on the screenshot, but it feeds the i2c, and not in my usecase.

I am considering writing this myself, but i am just getting into rust.

[burrbull]

dividers could be passed directly. See

stm32f1xx-hal/examples/adc_temperature.rs

Lines 27 to 36 in 6ff9c63

	// Alternative configuration using dividers and multipliers directly
	let clocks = rcc.cfgr.freeze_with_config(rcc::Config {
	hse: Some(8_000_000),
	pllmul: Some(7),
	hpre: rcc::HPre::DIV1,
	ppre1: rcc::PPre::DIV2,
	ppre2: rcc::PPre::DIV1,
	usbpre: rcc::UsbPre::DIV1_5,
	adcpre: rcc::AdcPre::DIV2,
	}, &mut flash.acr);*/

But you are right PLL3 is absent. You need to make PR to support it.