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| 1 | +/* |
| 2 | +* Copyright (c) 2017, Intel Corporation |
| 3 | +* |
| 4 | +* Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | +* copy of this software and associated documentation files (the "Software"), |
| 6 | +* to deal in the Software without restriction, including without limitation |
| 7 | +* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | +* and/or sell copies of the Software, and to permit persons to whom the |
| 9 | +* Software is furnished to do so, subject to the following conditions: |
| 10 | +* |
| 11 | +* The above copyright notice and this permission notice shall be included |
| 12 | +* in all copies or substantial portions of the Software. |
| 13 | +* |
| 14 | +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 15 | +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | +* OTHER DEALINGS IN THE SOFTWARE. |
| 21 | +*/ |
| 22 | +#include <string.h> |
| 23 | +#define LOCAL_I915_PARAM_HAS_HUC 42 |
| 24 | +struct DeviceConfig |
| 25 | +{ |
| 26 | + uint64_t aperture_size; //DRM_IOCTL_I915_GEM_GET_APERTURE |
| 27 | + //below is for DRM_IOCTL_I915_GETPARAM |
| 28 | + uint32_t DeviceId; //I915_PARAM_CHIPSET_ID |
| 29 | + uint32_t revision; //I915_PARAM_REVISION |
| 30 | + union { |
| 31 | + uint32_t flags; //Should put this before the struct, otherwise, it would be error in libdrm. |
| 32 | + struct { |
| 33 | + uint32_t has_exec2:1; //I915_PARAM_HAS_EXECBUF2 |
| 34 | + uint32_t has_bsd:1; //I915_PARAM_HAS_BSD |
| 35 | + uint32_t has_blt:1; //I915_PARAM_HAS_BLT |
| 36 | + uint32_t has_relaxed_fencing:1; //I915_PARAM_HAS_RELAXED_FENCING |
| 37 | + |
| 38 | + uint32_t has_wait_timeout:1; //I915_PARAM_HAS_WAIT_TIMEOUT |
| 39 | + uint32_t has_llc:1; //I915_PARAM_HAS_LLC |
| 40 | + uint32_t has_vebox:1; //I915_PARAM_HAS_VEBOX |
| 41 | + uint32_t has_ext_mmap:1; //I915_PARAM_MMAP_VERSION |
| 42 | + |
| 43 | + uint32_t has_exec_softpin:1; //I915_PARAM_HAS_EXEC_SOFTPIN |
| 44 | + uint32_t has_bsd2:1; //I915_PARAM_HAS_BSD |
| 45 | + uint32_t has_huc:1; //I915_PARAM_HAS_HUC |
| 46 | + |
| 47 | + uint32_t reserved:21; |
| 48 | + }; |
| 49 | + }; |
| 50 | + |
| 51 | + //uint32_t mmap_version; //I915_PARAM_MMAP_VERSION |
| 52 | + int32_t num_fences_avail; //I915_PARAM_NUM_FENCES_AVAIL |
| 53 | + int32_t aliasing_ppgtt; //I915_PARAM_HAS_ALIASING_PPGTT |
| 54 | + int32_t subslice_total; //I915_PARAM_SUBSLICE_TOTAL |
| 55 | + int32_t eu_total; //I915_PARAM_EU_TOTAL |
| 56 | + |
| 57 | + uint64_t edram_reg; |
| 58 | +/* |
| 59 | + void operator = (DeviceConfig &Dev2){ |
| 60 | + memcpy(this, &Dev2, sizeof(DeviceConfig)); |
| 61 | + };*/ |
| 62 | +} const DeviceConfigTable [] = { |
| 63 | +#define DEVICECONFIG( aper, devId, rev, flags, fences,ppgtt,subslice, eu, edram_reg ) { aper, devId, rev, flags, fences,ppgtt,subslice, eu, edram_reg}, |
| 64 | +/* |
| 65 | + * aperture_size, DeviceId, flags(), num_fences_avail, aliasing_ppgtt, subslice_total, eu_total, edram_reg, |
| 66 | + */ |
| 67 | +DEVICECONFIG( 4286468096, 0x191e, 0x7, 0x01ff, 32, 3, 3, 24, 0 ) //SKL |
| 68 | +DEVICECONFIG( 4267114496, 0x5a84, 0xb, 0x03df, 32, 3, 3, 18, 0x0 ) //BXT |
| 69 | +DEVICECONFIG( 4248690688, 0x1606, 0x9, 0x03ff, 32, 3, 2, 12, 0x0 ) //BDW |
| 70 | +DEVICECONFIG( 4259069952, 0x5a49, 0x3, 0x3ff, 32, 3, 2, 16, 0x0 ) //CNL |
| 71 | + |
| 72 | +#undef DEVICECONFIG |
| 73 | + { 0, 0, 0, 0, 0, 0, 0, 0, 0} |
| 74 | +}; |
| 75 | +typedef struct DeviceConfig DeviceConfig_t; |
| 76 | + |
| 77 | +typedef enum{ |
| 78 | + igfxSKLAKE = 0, |
| 79 | + igfxBROXTON = 1, |
| 80 | + igfxBROADWELL = 2, |
| 81 | + igfxCANNONLAKE = 3, |
| 82 | + igfx_MAX |
| 83 | +}Platform_t; |
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